485 lines
12 KiB
C
485 lines
12 KiB
C
/*
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* arch/arm/mach-ep93xx/core.c
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* Core routines for Cirrus EP93xx chips.
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*
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* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
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*
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* Thanks go to Michael Burian and Ray Lehtiniemi for their key
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* role in the ep93xx linux community.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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#include <linux/bitops.h>
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#include <linux/serial.h>
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#include <linux/serial_8250.h>
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#include <linux/serial_core.h>
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#include <linux/device.h>
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#include <linux/mm.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/delay.h>
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#include <linux/termios.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/serial.h>
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#include <asm/types.h>
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#include <asm/setup.h>
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#include <asm/memory.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/tlbflush.h>
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#include <asm/pgtable.h>
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#include <asm/io.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/gpio.h>
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#include <asm/hardware/vic.h>
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/*************************************************************************
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* Static I/O mappings that are needed for all EP93xx platforms
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*************************************************************************/
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static struct map_desc ep93xx_io_desc[] __initdata = {
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{
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.virtual = EP93XX_AHB_VIRT_BASE,
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.pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
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.length = EP93XX_AHB_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = EP93XX_APB_VIRT_BASE,
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.pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
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.length = EP93XX_APB_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init ep93xx_map_io(void)
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{
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iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
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}
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/*************************************************************************
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* Timer handling for EP93xx
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*************************************************************************
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* The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
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* 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
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* an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
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* is free-running, and can't generate interrupts.
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*
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* The 508 kHz timers are ideal for use for the timer interrupt, as the
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* most common values of HZ divide 508 kHz nicely. We pick one of the 16
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* bit timers (timer 1) since we don't need more than 16 bits of reload
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* value as long as HZ >= 8.
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*
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* The higher clock rate of timer 4 makes it a better choice than the
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* other timers for use in gettimeoffset(), while the fact that it can't
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* generate interrupts means we don't have to worry about not being able
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* to use this timer for something else. We also use timer 4 for keeping
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* track of lost jiffies.
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*/
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static unsigned int last_jiffy_time;
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#define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
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static int ep93xx_timer_interrupt(int irq, void *dev_id)
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{
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write_seqlock(&xtime_lock);
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__raw_writel(1, EP93XX_TIMER1_CLEAR);
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while ((signed long)
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(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
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>= TIMER4_TICKS_PER_JIFFY) {
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last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
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timer_tick();
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}
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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static struct irqaction ep93xx_timer_irq = {
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.name = "ep93xx timer",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = ep93xx_timer_interrupt,
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};
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static void __init ep93xx_timer_init(void)
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{
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/* Enable periodic HZ timer. */
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__raw_writel(0x48, EP93XX_TIMER1_CONTROL);
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__raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
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__raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
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/* Enable lost jiffy timer. */
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__raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
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setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
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}
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static unsigned long ep93xx_gettimeoffset(void)
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{
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int offset;
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offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
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/* Calculate (1000000 / 983040) * offset. */
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return offset + (53 * offset / 3072);
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}
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struct sys_timer ep93xx_timer = {
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.init = ep93xx_timer_init,
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.offset = ep93xx_gettimeoffset,
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};
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/*************************************************************************
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* GPIO handling for EP93xx
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*************************************************************************/
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static unsigned char gpio_int_enable[2];
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static unsigned char gpio_int_type1[2];
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static unsigned char gpio_int_type2[2];
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static void update_gpio_ab_int_params(int port)
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{
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if (port == 0) {
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__raw_writeb(0, EP93XX_GPIO_A_INT_ENABLE);
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__raw_writeb(gpio_int_type2[0], EP93XX_GPIO_A_INT_TYPE2);
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__raw_writeb(gpio_int_type1[0], EP93XX_GPIO_A_INT_TYPE1);
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__raw_writeb(gpio_int_enable[0], EP93XX_GPIO_A_INT_ENABLE);
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} else if (port == 1) {
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__raw_writeb(0, EP93XX_GPIO_B_INT_ENABLE);
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__raw_writeb(gpio_int_type2[1], EP93XX_GPIO_B_INT_TYPE2);
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__raw_writeb(gpio_int_type1[1], EP93XX_GPIO_B_INT_TYPE1);
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__raw_writeb(gpio_int_enable[1], EP93XX_GPIO_B_INT_ENABLE);
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}
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}
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static unsigned char data_register_offset[8] = {
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0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40,
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};
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static unsigned char data_direction_register_offset[8] = {
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0x10, 0x14, 0x18, 0x1c, 0x24, 0x34, 0x3c, 0x44,
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};
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void gpio_line_config(int line, int direction)
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{
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unsigned int data_direction_register;
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unsigned long flags;
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unsigned char v;
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data_direction_register =
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EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
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local_irq_save(flags);
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if (direction == GPIO_OUT) {
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if (line >= 0 && line < 16) {
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gpio_int_enable[line >> 3] &= ~(1 << (line & 7));
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update_gpio_ab_int_params(line >> 3);
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}
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v = __raw_readb(data_direction_register);
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v |= 1 << (line & 7);
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__raw_writeb(v, data_direction_register);
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} else if (direction == GPIO_IN) {
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v = __raw_readb(data_direction_register);
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v &= ~(1 << (line & 7));
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__raw_writeb(v, data_direction_register);
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}
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(gpio_line_config);
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int gpio_line_get(int line)
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{
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unsigned int data_register;
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data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
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return !!(__raw_readb(data_register) & (1 << (line & 7)));
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}
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EXPORT_SYMBOL(gpio_line_get);
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void gpio_line_set(int line, int value)
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{
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unsigned int data_register;
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unsigned long flags;
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unsigned char v;
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data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
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local_irq_save(flags);
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if (value == EP93XX_GPIO_HIGH) {
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v = __raw_readb(data_register);
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v |= 1 << (line & 7);
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__raw_writeb(v, data_register);
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} else if (value == EP93XX_GPIO_LOW) {
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v = __raw_readb(data_register);
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v &= ~(1 << (line & 7));
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__raw_writeb(v, data_register);
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}
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL(gpio_line_set);
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/*************************************************************************
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* EP93xx IRQ handling
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*************************************************************************/
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static void ep93xx_gpio_ab_irq_handler(unsigned int irq,
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struct irq_desc *desc)
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{
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unsigned char status;
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int i;
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status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
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for (i = 0; i < 8; i++) {
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if (status & (1 << i)) {
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desc = irq_desc + IRQ_EP93XX_GPIO(0) + i;
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desc_handle_irq(IRQ_EP93XX_GPIO(0) + i, desc);
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}
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}
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status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
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for (i = 0; i < 8; i++) {
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if (status & (1 << i)) {
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desc = irq_desc + IRQ_EP93XX_GPIO(8) + i;
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desc_handle_irq(IRQ_EP93XX_GPIO(8) + i, desc);
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}
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}
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}
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static void ep93xx_gpio_ab_irq_mask_ack(unsigned int irq)
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{
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int line = irq - IRQ_EP93XX_GPIO(0);
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int port = line >> 3;
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gpio_int_enable[port] &= ~(1 << (line & 7));
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update_gpio_ab_int_params(port);
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if (line >> 3) {
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__raw_writel(1 << (line & 7), EP93XX_GPIO_B_INT_ACK);
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} else {
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__raw_writel(1 << (line & 7), EP93XX_GPIO_A_INT_ACK);
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}
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}
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static void ep93xx_gpio_ab_irq_mask(unsigned int irq)
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{
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int line = irq - IRQ_EP93XX_GPIO(0);
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int port = line >> 3;
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gpio_int_enable[port] &= ~(1 << (line & 7));
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update_gpio_ab_int_params(port);
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}
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static void ep93xx_gpio_ab_irq_unmask(unsigned int irq)
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{
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int line = irq - IRQ_EP93XX_GPIO(0);
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int port = line >> 3;
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gpio_int_enable[port] |= 1 << (line & 7);
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update_gpio_ab_int_params(port);
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}
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/*
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* gpio_int_type1 controls whether the interrupt is level (0) or
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* edge (1) triggered, while gpio_int_type2 controls whether it
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* triggers on low/falling (0) or high/rising (1).
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*/
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static int ep93xx_gpio_ab_irq_type(unsigned int irq, unsigned int type)
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{
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int port;
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int line;
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line = irq - IRQ_EP93XX_GPIO(0);
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gpio_line_config(line, GPIO_IN);
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port = line >> 3;
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line &= 7;
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if (type & IRQT_RISING) {
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gpio_int_type1[port] |= 1 << line;
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gpio_int_type2[port] |= 1 << line;
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} else if (type & IRQT_FALLING) {
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gpio_int_type1[port] |= 1 << line;
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gpio_int_type2[port] &= ~(1 << line);
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} else if (type & IRQT_HIGH) {
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gpio_int_type1[port] &= ~(1 << line);
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gpio_int_type2[port] |= 1 << line;
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} else if (type & IRQT_LOW) {
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gpio_int_type1[port] &= ~(1 << line);
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gpio_int_type2[port] &= ~(1 << line);
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}
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update_gpio_ab_int_params(port);
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return 0;
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}
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static struct irq_chip ep93xx_gpio_ab_irq_chip = {
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.ack = ep93xx_gpio_ab_irq_mask_ack,
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.mask = ep93xx_gpio_ab_irq_mask,
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.unmask = ep93xx_gpio_ab_irq_unmask,
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.set_type = ep93xx_gpio_ab_irq_type,
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};
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void __init ep93xx_init_irq(void)
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{
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int irq;
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vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
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vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
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for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) {
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set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
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}
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/*************************************************************************
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* EP93xx peripheral handling
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*************************************************************************/
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#define EP93XX_UART_MCR_OFFSET (0x0100)
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static void ep93xx_uart_set_mctrl(struct amba_device *dev,
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void __iomem *base, unsigned int mctrl)
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{
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unsigned int mcr;
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mcr = 0;
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if (!(mctrl & TIOCM_RTS))
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mcr |= 2;
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if (!(mctrl & TIOCM_DTR))
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mcr |= 1;
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__raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
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}
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static struct amba_pl010_data ep93xx_uart_data = {
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.set_mctrl = ep93xx_uart_set_mctrl,
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};
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static struct amba_device uart1_device = {
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.dev = {
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.bus_id = "apb:uart1",
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.platform_data = &ep93xx_uart_data,
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},
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.res = {
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.start = EP93XX_UART1_PHYS_BASE,
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.end = EP93XX_UART1_PHYS_BASE + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_EP93XX_UART1, NO_IRQ },
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.periphid = 0x00041010,
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};
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static struct amba_device uart2_device = {
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.dev = {
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.bus_id = "apb:uart2",
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.platform_data = &ep93xx_uart_data,
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},
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.res = {
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.start = EP93XX_UART2_PHYS_BASE,
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.end = EP93XX_UART2_PHYS_BASE + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_EP93XX_UART2, NO_IRQ },
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.periphid = 0x00041010,
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};
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static struct amba_device uart3_device = {
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.dev = {
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.bus_id = "apb:uart3",
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.platform_data = &ep93xx_uart_data,
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},
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.res = {
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.start = EP93XX_UART3_PHYS_BASE,
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.end = EP93XX_UART3_PHYS_BASE + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_EP93XX_UART3, NO_IRQ },
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.periphid = 0x00041010,
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};
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static struct platform_device ep93xx_rtc_device = {
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.name = "ep93xx-rtc",
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.id = -1,
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.num_resources = 0,
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};
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static struct resource ep93xx_ohci_resources[] = {
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[0] = {
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.start = EP93XX_USB_PHYS_BASE,
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.end = EP93XX_USB_PHYS_BASE + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_EP93XX_USB,
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.end = IRQ_EP93XX_USB,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device ep93xx_ohci_device = {
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.name = "ep93xx-ohci",
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.id = -1,
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.dev = {
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.dma_mask = (void *)0xffffffff,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
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.resource = ep93xx_ohci_resources,
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};
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void __init ep93xx_init_devices(void)
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{
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unsigned int v;
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ep93xx_clock_init();
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/*
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* Disallow access to MaverickCrunch initially.
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*/
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v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
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v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
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__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
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__raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
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amba_device_register(&uart1_device, &iomem_resource);
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amba_device_register(&uart2_device, &iomem_resource);
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amba_device_register(&uart3_device, &iomem_resource);
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platform_device_register(&ep93xx_rtc_device);
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platform_device_register(&ep93xx_ohci_device);
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#ifdef CONFIG_CRUNCH
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elf_hwcap |= HWCAP_CRUNCH;
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#endif
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}
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