316 lines
8.5 KiB
C
316 lines
8.5 KiB
C
/*
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* MAXIM MAX77620 GPIO driver
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/max77620.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
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struct max77620_gpio {
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struct gpio_chip gpio_chip;
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struct regmap *rmap;
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struct device *dev;
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int gpio_irq;
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int irq_base;
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int gpio_base;
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};
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static const struct regmap_irq max77620_gpio_irqs[] = {
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[0] = {
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.mask = MAX77620_IRQ_LVL2_GPIO_EDGE0,
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.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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.reg_offset = 0,
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.type_reg_offset = 0,
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},
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[1] = {
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.mask = MAX77620_IRQ_LVL2_GPIO_EDGE1,
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.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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.reg_offset = 0,
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.type_reg_offset = 1,
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},
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[2] = {
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.mask = MAX77620_IRQ_LVL2_GPIO_EDGE2,
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.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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.reg_offset = 0,
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.type_reg_offset = 2,
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},
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[3] = {
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.mask = MAX77620_IRQ_LVL2_GPIO_EDGE3,
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.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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.reg_offset = 0,
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.type_reg_offset = 3,
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},
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[4] = {
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.mask = MAX77620_IRQ_LVL2_GPIO_EDGE4,
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.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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.reg_offset = 0,
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.type_reg_offset = 4,
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},
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[5] = {
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.mask = MAX77620_IRQ_LVL2_GPIO_EDGE5,
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.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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.reg_offset = 0,
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.type_reg_offset = 5,
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},
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[6] = {
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.mask = MAX77620_IRQ_LVL2_GPIO_EDGE6,
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.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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.reg_offset = 0,
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.type_reg_offset = 6,
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},
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[7] = {
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.mask = MAX77620_IRQ_LVL2_GPIO_EDGE7,
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.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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.reg_offset = 0,
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.type_reg_offset = 7,
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},
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};
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static struct regmap_irq_chip max77620_gpio_irq_chip = {
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.name = "max77620-gpio",
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.irqs = max77620_gpio_irqs,
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.num_irqs = ARRAY_SIZE(max77620_gpio_irqs),
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.num_regs = 1,
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.num_type_reg = 8,
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.irq_reg_stride = 1,
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.type_reg_stride = 1,
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.status_base = MAX77620_REG_IRQ_LVL2_GPIO,
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.type_base = MAX77620_REG_GPIO0,
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};
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static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
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{
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struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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int ret;
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ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_DIR_MASK,
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MAX77620_CNFG_GPIO_DIR_INPUT);
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if (ret < 0)
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dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
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return ret;
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}
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static int max77620_gpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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unsigned int val;
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int ret;
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ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val);
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if (ret < 0) {
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dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
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return ret;
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}
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if (val & MAX77620_CNFG_GPIO_DIR_MASK)
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return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
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else
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return !!(val & MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK);
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}
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static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned int offset,
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int value)
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{
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struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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u8 val;
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int ret;
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val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
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MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
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ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
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if (ret < 0) {
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dev_err(mgpio->dev, "CNFG_GPIOx val update failed: %d\n", ret);
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return ret;
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}
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ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_DIR_MASK,
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MAX77620_CNFG_GPIO_DIR_OUTPUT);
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if (ret < 0)
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dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
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return ret;
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}
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static int max77620_gpio_set_debounce(struct gpio_chip *gc,
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unsigned int offset,
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unsigned int debounce)
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{
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struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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u8 val;
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int ret;
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switch (debounce) {
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case 0:
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val = MAX77620_CNFG_GPIO_DBNC_None;
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break;
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case 1 ... 8:
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val = MAX77620_CNFG_GPIO_DBNC_8ms;
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break;
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case 9 ... 16:
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val = MAX77620_CNFG_GPIO_DBNC_16ms;
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break;
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case 17 ... 32:
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val = MAX77620_CNFG_GPIO_DBNC_32ms;
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break;
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default:
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dev_err(mgpio->dev, "Illegal value %u\n", debounce);
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return -EINVAL;
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}
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ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_DBNC_MASK, val);
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if (ret < 0)
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dev_err(mgpio->dev, "CNFG_GPIOx_DBNC update failed: %d\n", ret);
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return ret;
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}
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static void max77620_gpio_set(struct gpio_chip *gc, unsigned int offset,
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int value)
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{
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struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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u8 val;
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int ret;
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val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
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MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
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ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
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if (ret < 0)
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dev_err(mgpio->dev, "CNFG_GPIO_OUT update failed: %d\n", ret);
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}
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static int max77620_gpio_set_single_ended(struct gpio_chip *gc,
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unsigned int offset,
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enum single_ended_mode mode)
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{
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struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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switch (mode) {
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case LINE_MODE_OPEN_DRAIN:
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return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_DRV_MASK,
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MAX77620_CNFG_GPIO_DRV_OPENDRAIN);
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case LINE_MODE_PUSH_PULL:
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return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
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MAX77620_CNFG_GPIO_DRV_MASK,
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MAX77620_CNFG_GPIO_DRV_PUSHPULL);
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default:
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break;
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}
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return -ENOTSUPP;
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}
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static int max77620_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
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{
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struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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struct max77620_chip *chip = dev_get_drvdata(mgpio->dev->parent);
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return regmap_irq_get_virq(chip->gpio_irq_data, offset);
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}
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static int max77620_gpio_probe(struct platform_device *pdev)
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{
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struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
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struct max77620_gpio *mgpio;
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int gpio_irq;
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int ret;
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gpio_irq = platform_get_irq(pdev, 0);
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if (gpio_irq <= 0) {
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dev_err(&pdev->dev, "GPIO irq not available %d\n", gpio_irq);
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return -ENODEV;
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}
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mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
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if (!mgpio)
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return -ENOMEM;
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mgpio->rmap = chip->rmap;
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mgpio->dev = &pdev->dev;
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mgpio->gpio_irq = gpio_irq;
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mgpio->gpio_chip.label = pdev->name;
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mgpio->gpio_chip.parent = &pdev->dev;
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mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
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mgpio->gpio_chip.get = max77620_gpio_get;
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mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
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mgpio->gpio_chip.set_debounce = max77620_gpio_set_debounce;
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mgpio->gpio_chip.set = max77620_gpio_set;
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mgpio->gpio_chip.set_single_ended = max77620_gpio_set_single_ended;
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mgpio->gpio_chip.to_irq = max77620_gpio_to_irq;
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mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
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mgpio->gpio_chip.can_sleep = 1;
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mgpio->gpio_chip.base = -1;
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mgpio->irq_base = -1;
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#ifdef CONFIG_OF_GPIO
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mgpio->gpio_chip.of_node = pdev->dev.parent->of_node;
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#endif
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platform_set_drvdata(pdev, mgpio);
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ret = devm_gpiochip_add_data(&pdev->dev, &mgpio->gpio_chip, mgpio);
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if (ret < 0) {
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dev_err(&pdev->dev, "gpio_init: Failed to add max77620_gpio\n");
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return ret;
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}
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mgpio->gpio_base = mgpio->gpio_chip.base;
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ret = devm_regmap_add_irq_chip(&pdev->dev, chip->rmap, mgpio->gpio_irq,
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IRQF_ONESHOT, mgpio->irq_base,
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&max77620_gpio_irq_chip,
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&chip->gpio_irq_data);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to add gpio irq_chip %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct platform_device_id max77620_gpio_devtype[] = {
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{ .name = "max77620-gpio", },
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{},
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};
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MODULE_DEVICE_TABLE(platform, max77620_gpio_devtype);
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static struct platform_driver max77620_gpio_driver = {
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.driver.name = "max77620-gpio",
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.probe = max77620_gpio_probe,
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.id_table = max77620_gpio_devtype,
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};
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module_platform_driver(max77620_gpio_driver);
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MODULE_DESCRIPTION("GPIO interface for MAX77620 and MAX20024 PMIC");
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MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
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MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
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MODULE_ALIAS("platform:max77620-gpio");
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MODULE_LICENSE("GPL v2");
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