634 lines
15 KiB
C
634 lines
15 KiB
C
/*
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* Freescale Memory Controller kernel module
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*
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* Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
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* ARM-based Layerscape SoCs including LS2xxx. Originally split
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* out from mpc85xx_edac EDAC driver.
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*
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* Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
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*
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* Author: Dave Jiang <djiang@mvista.com>
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*
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* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/ctype.h>
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#include <linux/io.h>
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#include <linux/mod_devicetable.h>
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#include <linux/edac.h>
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#include <linux/smp.h>
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#include <linux/gfp.h>
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include "edac_module.h"
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#include "edac_core.h"
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#include "fsl_ddr_edac.h"
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#define EDAC_MOD_STR "fsl_ddr_edac"
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static int edac_mc_idx;
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static u32 orig_ddr_err_disable;
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static u32 orig_ddr_err_sbe;
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static bool little_endian;
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static inline u32 ddr_in32(void __iomem *addr)
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{
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return little_endian ? ioread32(addr) : ioread32be(addr);
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}
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static inline void ddr_out32(void __iomem *addr, u32 value)
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{
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if (little_endian)
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iowrite32(value, addr);
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else
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iowrite32be(value, addr);
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}
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/************************ MC SYSFS parts ***********************************/
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#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
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static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
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struct device_attribute *mattr,
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char *data)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI));
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}
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static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
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struct device_attribute *mattr,
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char *data)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO));
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}
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static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
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struct device_attribute *mattr,
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char *data)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
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}
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static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
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struct device_attribute *mattr,
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const char *data, size_t count)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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unsigned long val;
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int rc;
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if (isdigit(*data)) {
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rc = kstrtoul(data, 0, &val);
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if (rc)
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return rc;
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ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI, val);
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return count;
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}
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return 0;
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}
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static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
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struct device_attribute *mattr,
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const char *data, size_t count)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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unsigned long val;
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int rc;
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if (isdigit(*data)) {
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rc = kstrtoul(data, 0, &val);
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if (rc)
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return rc;
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ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO, val);
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return count;
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}
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return 0;
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}
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static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
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struct device_attribute *mattr,
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const char *data, size_t count)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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unsigned long val;
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int rc;
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if (isdigit(*data)) {
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rc = kstrtoul(data, 0, &val);
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if (rc)
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return rc;
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ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT, val);
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return count;
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}
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return 0;
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}
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DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR,
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fsl_mc_inject_data_hi_show, fsl_mc_inject_data_hi_store);
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DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
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fsl_mc_inject_data_lo_show, fsl_mc_inject_data_lo_store);
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DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
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fsl_mc_inject_ctrl_show, fsl_mc_inject_ctrl_store);
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static struct attribute *fsl_ddr_dev_attrs[] = {
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&dev_attr_inject_data_hi.attr,
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&dev_attr_inject_data_lo.attr,
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&dev_attr_inject_ctrl.attr,
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NULL
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};
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ATTRIBUTE_GROUPS(fsl_ddr_dev);
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/**************************** MC Err device ***************************/
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/*
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* Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
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* MPC8572 User's Manual. Each line represents a syndrome bit column as a
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* 64-bit value, but split into an upper and lower 32-bit chunk. The labels
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* below correspond to Freescale's manuals.
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*/
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static unsigned int ecc_table[16] = {
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/* MSB LSB */
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/* [0:31] [32:63] */
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0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
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0x00ff00ff, 0x00fff0ff,
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0x0f0f0f0f, 0x0f0fff00,
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0x11113333, 0x7777000f,
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0x22224444, 0x8888222f,
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0x44448888, 0xffff4441,
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0x8888ffff, 0x11118882,
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0xffff1111, 0x22221114, /* Syndrome bit 0 */
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};
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/*
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* Calculate the correct ECC value for a 64-bit value specified by high:low
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*/
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static u8 calculate_ecc(u32 high, u32 low)
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{
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u32 mask_low;
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u32 mask_high;
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int bit_cnt;
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u8 ecc = 0;
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int i;
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int j;
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for (i = 0; i < 8; i++) {
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mask_high = ecc_table[i * 2];
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mask_low = ecc_table[i * 2 + 1];
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bit_cnt = 0;
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for (j = 0; j < 32; j++) {
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if ((mask_high >> j) & 1)
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bit_cnt ^= (high >> j) & 1;
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if ((mask_low >> j) & 1)
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bit_cnt ^= (low >> j) & 1;
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}
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ecc |= bit_cnt << i;
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}
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return ecc;
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}
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/*
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* Create the syndrome code which is generated if the data line specified by
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* 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
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* User's Manual and 9-61 in the MPC8572 User's Manual.
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*/
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static u8 syndrome_from_bit(unsigned int bit) {
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int i;
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u8 syndrome = 0;
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/*
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* Cycle through the upper or lower 32-bit portion of each value in
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* ecc_table depending on if 'bit' is in the upper or lower half of
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* 64-bit data.
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*/
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for (i = bit < 32; i < 16; i += 2)
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syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
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return syndrome;
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}
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/*
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* Decode data and ecc syndrome to determine what went wrong
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* Note: This can only decode single-bit errors
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*/
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static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
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int *bad_data_bit, int *bad_ecc_bit)
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{
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int i;
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u8 syndrome;
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*bad_data_bit = -1;
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*bad_ecc_bit = -1;
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/*
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* Calculate the ECC of the captured data and XOR it with the captured
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* ECC to find an ECC syndrome value we can search for
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*/
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syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
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/* Check if a data line is stuck... */
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for (i = 0; i < 64; i++) {
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if (syndrome == syndrome_from_bit(i)) {
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*bad_data_bit = i;
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return;
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}
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}
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/* If data is correct, check ECC bits for errors... */
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for (i = 0; i < 8; i++) {
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if ((syndrome >> i) & 0x1) {
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*bad_ecc_bit = i;
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return;
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}
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}
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}
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#define make64(high, low) (((u64)(high) << 32) | (low))
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static void fsl_mc_check(struct mem_ctl_info *mci)
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{
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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struct csrow_info *csrow;
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u32 bus_width;
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u32 err_detect;
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u32 syndrome;
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u64 err_addr;
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u32 pfn;
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int row_index;
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u32 cap_high;
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u32 cap_low;
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int bad_data_bit;
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int bad_ecc_bit;
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err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
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if (!err_detect)
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return;
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fsl_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
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err_detect);
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/* no more processing if not ECC bit errors */
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if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
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ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
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return;
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}
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syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
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/* Mask off appropriate bits of syndrome based on bus width */
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bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
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DSC_DBW_MASK) ? 32 : 64;
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if (bus_width == 64)
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syndrome &= 0xff;
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else
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syndrome &= 0xffff;
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err_addr = make64(
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ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
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ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
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pfn = err_addr >> PAGE_SHIFT;
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for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
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csrow = mci->csrows[row_index];
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if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
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break;
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}
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cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
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cap_low = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
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/*
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* Analyze single-bit errors on 64-bit wide buses
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* TODO: Add support for 32-bit wide buses
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*/
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if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
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sbe_ecc_decode(cap_high, cap_low, syndrome,
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&bad_data_bit, &bad_ecc_bit);
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if (bad_data_bit != -1)
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fsl_mc_printk(mci, KERN_ERR,
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"Faulty Data bit: %d\n", bad_data_bit);
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if (bad_ecc_bit != -1)
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fsl_mc_printk(mci, KERN_ERR,
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"Faulty ECC bit: %d\n", bad_ecc_bit);
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fsl_mc_printk(mci, KERN_ERR,
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"Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
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cap_high ^ (1 << (bad_data_bit - 32)),
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cap_low ^ (1 << bad_data_bit),
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syndrome ^ (1 << bad_ecc_bit));
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}
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fsl_mc_printk(mci, KERN_ERR,
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"Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
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cap_high, cap_low, syndrome);
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fsl_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
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fsl_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
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/* we are out of range */
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if (row_index == mci->nr_csrows)
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fsl_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
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if (err_detect & DDR_EDE_SBE)
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
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pfn, err_addr & ~PAGE_MASK, syndrome,
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row_index, 0, -1,
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mci->ctl_name, "");
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if (err_detect & DDR_EDE_MBE)
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
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pfn, err_addr & ~PAGE_MASK, syndrome,
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row_index, 0, -1,
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mci->ctl_name, "");
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ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
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}
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static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
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{
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struct mem_ctl_info *mci = dev_id;
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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u32 err_detect;
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err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
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if (!err_detect)
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return IRQ_NONE;
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fsl_mc_check(mci);
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return IRQ_HANDLED;
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}
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static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
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{
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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struct csrow_info *csrow;
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struct dimm_info *dimm;
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u32 sdram_ctl;
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u32 sdtype;
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enum mem_type mtype;
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u32 cs_bnds;
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int index;
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sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
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sdtype = sdram_ctl & DSC_SDTYPE_MASK;
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if (sdram_ctl & DSC_RD_EN) {
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switch (sdtype) {
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case 0x02000000:
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mtype = MEM_RDDR;
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break;
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case 0x03000000:
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mtype = MEM_RDDR2;
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break;
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case 0x07000000:
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mtype = MEM_RDDR3;
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break;
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case 0x05000000:
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mtype = MEM_RDDR4;
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break;
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default:
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mtype = MEM_UNKNOWN;
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break;
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}
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} else {
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switch (sdtype) {
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case 0x02000000:
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mtype = MEM_DDR;
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break;
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case 0x03000000:
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mtype = MEM_DDR2;
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break;
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case 0x07000000:
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mtype = MEM_DDR3;
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break;
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case 0x05000000:
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mtype = MEM_DDR4;
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break;
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default:
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mtype = MEM_UNKNOWN;
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break;
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}
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}
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for (index = 0; index < mci->nr_csrows; index++) {
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u32 start;
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u32 end;
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csrow = mci->csrows[index];
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dimm = csrow->channels[0]->dimm;
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cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
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(index * FSL_MC_CS_BNDS_OFS));
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start = (cs_bnds & 0xffff0000) >> 16;
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end = (cs_bnds & 0x0000ffff);
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if (start == end)
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continue; /* not populated */
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start <<= (24 - PAGE_SHIFT);
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end <<= (24 - PAGE_SHIFT);
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end |= (1 << (24 - PAGE_SHIFT)) - 1;
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csrow->first_page = start;
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csrow->last_page = end;
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dimm->nr_pages = end + 1 - start;
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dimm->grain = 8;
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dimm->mtype = mtype;
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dimm->dtype = DEV_UNKNOWN;
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if (sdram_ctl & DSC_X32_EN)
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dimm->dtype = DEV_X32;
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dimm->edac_mode = EDAC_SECDED;
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}
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}
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int fsl_mc_err_probe(struct platform_device *op)
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{
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struct mem_ctl_info *mci;
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struct edac_mc_layer layers[2];
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struct fsl_mc_pdata *pdata;
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struct resource r;
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u32 sdram_ctl;
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int res;
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if (!devres_open_group(&op->dev, fsl_mc_err_probe, GFP_KERNEL))
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return -ENOMEM;
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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layers[0].size = 4;
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layers[0].is_virt_csrow = true;
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layers[1].type = EDAC_MC_LAYER_CHANNEL;
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layers[1].size = 1;
|
|
layers[1].is_virt_csrow = false;
|
|
mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
|
|
sizeof(*pdata));
|
|
if (!mci) {
|
|
devres_release_group(&op->dev, fsl_mc_err_probe);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pdata = mci->pvt_info;
|
|
pdata->name = "fsl_mc_err";
|
|
mci->pdev = &op->dev;
|
|
pdata->edac_idx = edac_mc_idx++;
|
|
dev_set_drvdata(mci->pdev, mci);
|
|
mci->ctl_name = pdata->name;
|
|
mci->dev_name = pdata->name;
|
|
|
|
/*
|
|
* Get the endianness of DDR controller registers.
|
|
* Default is big endian.
|
|
*/
|
|
little_endian = of_property_read_bool(op->dev.of_node, "little-endian");
|
|
|
|
res = of_address_to_resource(op->dev.of_node, 0, &r);
|
|
if (res) {
|
|
pr_err("%s: Unable to get resource for MC err regs\n",
|
|
__func__);
|
|
goto err;
|
|
}
|
|
|
|
if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
|
|
pdata->name)) {
|
|
pr_err("%s: Error while requesting mem region\n",
|
|
__func__);
|
|
res = -EBUSY;
|
|
goto err;
|
|
}
|
|
|
|
pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
|
|
if (!pdata->mc_vbase) {
|
|
pr_err("%s: Unable to setup MC err regs\n", __func__);
|
|
res = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
|
|
if (!(sdram_ctl & DSC_ECC_EN)) {
|
|
/* no ECC */
|
|
pr_warn("%s: No ECC DIMMs discovered\n", __func__);
|
|
res = -ENODEV;
|
|
goto err;
|
|
}
|
|
|
|
edac_dbg(3, "init mci\n");
|
|
mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR |
|
|
MEM_FLAG_DDR2 | MEM_FLAG_RDDR2 |
|
|
MEM_FLAG_DDR3 | MEM_FLAG_RDDR3 |
|
|
MEM_FLAG_DDR4 | MEM_FLAG_RDDR4;
|
|
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
|
|
mci->edac_cap = EDAC_FLAG_SECDED;
|
|
mci->mod_name = EDAC_MOD_STR;
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_POLL)
|
|
mci->edac_check = fsl_mc_check;
|
|
|
|
mci->ctl_page_to_phys = NULL;
|
|
|
|
mci->scrub_mode = SCRUB_SW_SRC;
|
|
|
|
fsl_ddr_init_csrows(mci);
|
|
|
|
/* store the original error disable bits */
|
|
orig_ddr_err_disable = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
|
|
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
|
|
|
|
/* clear all error bits */
|
|
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
|
|
|
|
res = edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups);
|
|
if (res) {
|
|
edac_dbg(3, "failed edac_mc_add_mc()\n");
|
|
goto err;
|
|
}
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_INT) {
|
|
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
|
|
DDR_EIE_MBEE | DDR_EIE_SBEE);
|
|
|
|
/* store the original error management threshold */
|
|
orig_ddr_err_sbe = ddr_in32(pdata->mc_vbase +
|
|
FSL_MC_ERR_SBE) & 0xff0000;
|
|
|
|
/* set threshold to 1 error per interrupt */
|
|
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
|
|
|
|
/* register interrupts */
|
|
pdata->irq = platform_get_irq(op, 0);
|
|
res = devm_request_irq(&op->dev, pdata->irq,
|
|
fsl_mc_isr,
|
|
IRQF_SHARED,
|
|
"[EDAC] MC err", mci);
|
|
if (res < 0) {
|
|
pr_err("%s: Unable to request irq %d for FSL DDR DRAM ERR\n",
|
|
__func__, pdata->irq);
|
|
res = -ENODEV;
|
|
goto err2;
|
|
}
|
|
|
|
pr_info(EDAC_MOD_STR " acquired irq %d for MC\n",
|
|
pdata->irq);
|
|
}
|
|
|
|
devres_remove_group(&op->dev, fsl_mc_err_probe);
|
|
edac_dbg(3, "success\n");
|
|
pr_info(EDAC_MOD_STR " MC err registered\n");
|
|
|
|
return 0;
|
|
|
|
err2:
|
|
edac_mc_del_mc(&op->dev);
|
|
err:
|
|
devres_release_group(&op->dev, fsl_mc_err_probe);
|
|
edac_mc_free(mci);
|
|
return res;
|
|
}
|
|
|
|
int fsl_mc_err_remove(struct platform_device *op)
|
|
{
|
|
struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
|
|
struct fsl_mc_pdata *pdata = mci->pvt_info;
|
|
|
|
edac_dbg(0, "\n");
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_INT) {
|
|
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
|
|
}
|
|
|
|
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
|
|
orig_ddr_err_disable);
|
|
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
|
|
|
|
edac_mc_del_mc(&op->dev);
|
|
edac_mc_free(mci);
|
|
return 0;
|
|
}
|