215 lines
6.5 KiB
C
215 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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// Copyright 2017 IBM Corp.
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#ifndef _MISC_OCXL_H_
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#define _MISC_OCXL_H_
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#include <linux/pci.h>
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/*
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* Opencapi drivers all need some common facilities, like parsing the
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* device configuration space, adding a Process Element to the Shared
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* Process Area, etc...
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*
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* The ocxl module provides a kernel API, to allow other drivers to
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* reuse common code. A bit like a in-kernel library.
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*/
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#define OCXL_AFU_NAME_SZ (24+1) /* add 1 for NULL termination */
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/*
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* The following 2 structures are a fairly generic way of representing
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* the configuration data for a function and AFU, as read from the
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* configuration space.
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*/
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struct ocxl_afu_config {
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u8 idx;
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int dvsec_afu_control_pos; /* offset of AFU control DVSEC */
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char name[OCXL_AFU_NAME_SZ];
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u8 version_major;
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u8 version_minor;
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u8 afuc_type;
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u8 afum_type;
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u8 profile;
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u8 global_mmio_bar; /* global MMIO area */
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u64 global_mmio_offset;
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u32 global_mmio_size;
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u8 pp_mmio_bar; /* per-process MMIO area */
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u64 pp_mmio_offset;
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u32 pp_mmio_stride;
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u8 log_mem_size;
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u8 pasid_supported_log;
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u16 actag_supported;
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};
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struct ocxl_fn_config {
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int dvsec_tl_pos; /* offset of the Transaction Layer DVSEC */
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int dvsec_function_pos; /* offset of the Function DVSEC */
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int dvsec_afu_info_pos; /* offset of the AFU information DVSEC */
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s8 max_pasid_log;
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s8 max_afu_index;
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};
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/*
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* Read the configuration space of a function and fill in a
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* ocxl_fn_config structure with all the function details
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*/
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extern int ocxl_config_read_function(struct pci_dev *dev,
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struct ocxl_fn_config *fn);
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/*
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* Check if an AFU index is valid for the given function.
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*
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* AFU indexes can be sparse, so a driver should check all indexes up
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* to the maximum found in the function description
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*/
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extern int ocxl_config_check_afu_index(struct pci_dev *dev,
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struct ocxl_fn_config *fn, int afu_idx);
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/*
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* Read the configuration space of a function for the AFU specified by
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* the index 'afu_idx'. Fills in a ocxl_afu_config structure
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*/
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extern int ocxl_config_read_afu(struct pci_dev *dev,
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struct ocxl_fn_config *fn,
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struct ocxl_afu_config *afu,
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u8 afu_idx);
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/*
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* Get the max PASID value that can be used by the function
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*/
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extern int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count);
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/*
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* Tell an AFU, by writing in the configuration space, the PASIDs that
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* it can use. Range starts at 'pasid_base' and its size is a multiple
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* of 2
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*
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* 'afu_control_offset' is the offset of the AFU control DVSEC which
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* can be found in the function configuration
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*/
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extern void ocxl_config_set_afu_pasid(struct pci_dev *dev,
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int afu_control_offset,
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int pasid_base, u32 pasid_count_log);
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/*
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* Get the actag configuration for the function:
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* 'base' is the first actag value that can be used.
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* 'enabled' it the number of actags available, starting from base.
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* 'supported' is the total number of actags desired by all the AFUs
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* of the function.
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*/
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extern int ocxl_config_get_actag_info(struct pci_dev *dev,
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u16 *base, u16 *enabled, u16 *supported);
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/*
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* Tell a function, by writing in the configuration space, the actags
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* it can use.
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*
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* 'func_offset' is the offset of the Function DVSEC that can found in
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* the function configuration
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*/
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extern void ocxl_config_set_actag(struct pci_dev *dev, int func_offset,
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u32 actag_base, u32 actag_count);
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/*
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* Tell an AFU, by writing in the configuration space, the actags it
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* can use.
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*
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* 'afu_control_offset' is the offset of the AFU control DVSEC for the
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* desired AFU. It can be found in the AFU configuration
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*/
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extern void ocxl_config_set_afu_actag(struct pci_dev *dev,
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int afu_control_offset,
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int actag_base, int actag_count);
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/*
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* Enable/disable an AFU, by writing in the configuration space.
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*
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* 'afu_control_offset' is the offset of the AFU control DVSEC for the
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* desired AFU. It can be found in the AFU configuration
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*/
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extern void ocxl_config_set_afu_state(struct pci_dev *dev,
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int afu_control_offset, int enable);
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/*
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* Set the Transaction Layer configuration in the configuration space.
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* Only needed for function 0.
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*
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* It queries the host TL capabilities, find some common ground
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* between the host and device, and set the Transaction Layer on both
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* accordingly.
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*/
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extern int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec);
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/*
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* Request an AFU to terminate a PASID.
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* Will return once the AFU has acked the request, or an error in case
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* of timeout.
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*
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* The hardware can only terminate one PASID at a time, so caller must
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* guarantee some kind of serialization.
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*
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* 'afu_control_offset' is the offset of the AFU control DVSEC for the
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* desired AFU. It can be found in the AFU configuration
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*/
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extern int ocxl_config_terminate_pasid(struct pci_dev *dev,
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int afu_control_offset, int pasid);
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/*
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* Set up the opencapi link for the function.
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*
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* When called for the first time for a link, it sets up the Shared
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* Process Area for the link and the interrupt handler to process
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* translation faults.
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*
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* Returns a 'link handle' that should be used for further calls for
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* the link
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*/
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extern int ocxl_link_setup(struct pci_dev *dev, int PE_mask,
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void **link_handle);
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/*
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* Remove the association between the function and its link.
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*/
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extern void ocxl_link_release(struct pci_dev *dev, void *link_handle);
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/*
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* Add a Process Element to the Shared Process Area for a link.
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* The process is defined by its PASID, pid, tid and its mm_struct.
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*
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* 'xsl_err_cb' is an optional callback if the driver wants to be
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* notified when the translation fault interrupt handler detects an
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* address error.
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* 'xsl_err_data' is an argument passed to the above callback, if
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* defined
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*/
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extern int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
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u64 amr, struct mm_struct *mm,
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void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr),
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void *xsl_err_data);
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/*
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* Remove a Process Element from the Shared Process Area for a link
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*/
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extern int ocxl_link_remove_pe(void *link_handle, int pasid);
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/*
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* Allocate an AFU interrupt associated to the link.
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*
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* 'hw_irq' is the hardware interrupt number
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* 'obj_handle' is the 64-bit object handle to be passed to the AFU to
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* trigger the interrupt.
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* On P9, 'obj_handle' is an address, which, if written, triggers the
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* interrupt. It is an MMIO address which needs to be remapped (one
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* page).
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*/
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extern int ocxl_link_irq_alloc(void *link_handle, int *hw_irq,
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u64 *obj_handle);
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/*
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* Free a previously allocated AFU interrupt
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*/
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extern void ocxl_link_free_irq(void *link_handle, int hw_irq);
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#endif /* _MISC_OCXL_H_ */
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