linux-sg2042/drivers/pinctrl/intel
Cristina Ciocan c8f5c4c7c8 pinctrl: baytrail: Add pin control data structures
In order to implement pin control for Baytrail, we need data
structures in which to store and pass along pin, group, function,
community and SOC data information.

Baytrail has 3 GPIO controllers. Add SCORE, NCORE and SUS
controller data:
- pins (for all controllers),
- pad map for pins (for all controllers; we need this since pads
  are not ordered),
- groups (for SCORE and SUS controllers),
- functions (for SCORE and SUS controllers),
- communities (for all controllers),
- soc specific data gathering all of the above and the ACPI UID
  (for all controllers)

This information is useful for pin control functionality.
NCORE data is lighter than the other two controllers' due to
lack of pin documentation in the public datasheet.

Datasheet:
http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html

Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-04-04 15:55:21 +02:00
..
Kconfig pinctrl: intel: Add Intel Broxton pin controller support 2015-10-27 13:32:13 +01:00
Makefile pinctrl: intel: Add Intel Broxton pin controller support 2015-10-27 13:32:13 +01:00
pinctrl-baytrail.c pinctrl: baytrail: Add pin control data structures 2016-04-04 15:55:21 +02:00
pinctrl-broxton.c pinctrl: intel: fix bug of register offset calculation 2015-12-10 23:01:41 +01:00
pinctrl-cherryview.c pinctrl: cherryview: use gpiochip data pointer 2016-01-05 14:14:48 +01:00
pinctrl-intel.c pinctrl: intel: Remove unneeded header includes 2016-02-12 13:56:57 +01:00
pinctrl-intel.h pinctrl: intel: fix bug of register offset calculation 2015-12-10 23:01:41 +01:00
pinctrl-sunrisepoint.c pinctrl: intel: fix bug of register offset calculation 2015-12-10 23:01:41 +01:00