223 lines
6.9 KiB
Plaintext
223 lines
6.9 KiB
Plaintext
Qualcomm QMP PHY controller
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===========================
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QMP phy controller supports physical layer functionality for a number of
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controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
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Required properties:
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- compatible: compatible list, contains:
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"qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
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"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
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"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
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"qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
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"qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
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"qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
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"qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
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"qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
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"qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
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- reg:
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- index 0: address and length of register set for PHY's common
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serdes block.
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- index 1: address and length of the DP_COM control block (for
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"qcom,sdm845-qmp-usb3-phy" only).
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- reg-names:
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- For "qcom,sdm845-qmp-usb3-phy":
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- Should be: "reg-base", "dp_com"
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- For all others:
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- The reg-names property shouldn't be defined.
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- #address-cells: must be 1
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- #size-cells: must be 1
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- ranges: must be present
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: "cfg_ahb" for phy config clock,
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"aux" for phy aux clock,
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"ref" for 19.2 MHz ref clk,
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"com_aux" for phy common block aux clock,
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"ref_aux" for phy reference aux clock,
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For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
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For "qcom,msm8996-qmp-pcie-phy" must contain:
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"aux", "cfg_ahb", "ref".
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For "qcom,msm8996-qmp-usb3-phy" must contain:
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"aux", "cfg_ahb", "ref".
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For "qcom,msm8998-qmp-usb3-phy" must contain:
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"aux", "cfg_ahb", "ref".
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For "qcom,msm8998-qmp-ufs-phy" must contain:
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"ref", "ref_aux".
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For "qcom,msm8998-qmp-pcie-phy" must contain:
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"aux", "cfg_ahb", "ref".
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For "qcom,sdm845-qmp-usb3-phy" must contain:
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"aux", "cfg_ahb", "ref", "com_aux".
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For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
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"aux", "cfg_ahb", "ref", "com_aux".
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For "qcom,sdm845-qmp-ufs-phy" must contain:
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"ref", "ref_aux".
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- resets: a list of phandles and reset controller specifier pairs,
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one for each entry in reset-names.
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- reset-names: "phy" for reset of phy block,
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"common" for phy common block reset,
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"cfg" for phy's ahb cfg block reset,
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"ufsphy" for the PHY reset in the UFS controller.
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For "qcom,ipq8074-qmp-pcie-phy" must contain:
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"phy", "common".
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For "qcom,msm8996-qmp-pcie-phy" must contain:
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"phy", "common", "cfg".
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For "qcom,msm8996-qmp-usb3-phy" must contain
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"phy", "common".
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For "qcom,msm8998-qmp-usb3-phy" must contain
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"phy", "common".
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For "qcom,msm8998-qmp-ufs-phy": must contain:
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"ufsphy".
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For "qcom,msm8998-qmp-pcie-phy" must contain:
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"phy", "common".
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For "qcom,sdm845-qmp-usb3-phy" must contain:
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"phy", "common".
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For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
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"phy", "common".
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For "qcom,sdm845-qmp-ufs-phy": must contain:
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"ufsphy".
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- vdda-phy-supply: Phandle to a regulator supply to PHY core block.
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- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
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Optional properties:
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- vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
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pll block.
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Required nodes:
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- Each device node of QMP phy is required to have as many child nodes as
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the number of lanes the PHY has.
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Required properties for child nodes of PCIe PHYs (one child per lane):
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- reg: list of offset and length pairs of register sets for PHY blocks -
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tx, rx, pcs, and pcs_misc (optional).
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- #phy-cells: must be 0
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Required properties for a single "lanes" child node of non-PCIe PHYs:
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- reg: list of offset and length pairs of register sets for PHY blocks
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For 1-lane devices:
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tx, rx, pcs, and (optionally) pcs_misc
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For 2-lane devices:
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tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc
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- #phy-cells: must be 0
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Required properties for child node of PCIe and USB3 qmp phys:
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: Must contain following:
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"pipe<lane-number>" for pipe clock specific to each lane.
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- clock-output-names: Name of the PHY clock that will be the parent for
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the above pipe clock.
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For "qcom,ipq8074-qmp-pcie-phy":
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- "pcie20_phy0_pipe_clk" Pipe Clock parent
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(or)
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"pcie20_phy1_pipe_clk"
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- #clock-cells: must be 0
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- Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
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gate-controlled by the gcc.
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Required properties for child node of PHYs with lane reset, AKA:
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"qcom,msm8996-qmp-pcie-phy"
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- resets: a list of phandles and reset controller specifier pairs,
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one for each entry in reset-names.
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- reset-names: Must contain following:
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"lane<lane-number>" for reset specific to each lane.
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Example:
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phy@34000 {
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compatible = "qcom,msm8996-qmp-pcie-phy";
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reg = <0x34000 0x488>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_CLKREF_CLK>;
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clock-names = "aux", "cfg_ahb", "ref";
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vdda-phy-supply = <&pm8994_l28>;
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vdda-pll-supply = <&pm8994_l12>;
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resets = <&gcc GCC_PCIE_PHY_BCR>,
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<&gcc GCC_PCIE_PHY_COM_BCR>,
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<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
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reset-names = "phy", "common", "cfg";
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pciephy_0: lane@35000 {
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reg = <0x35000 0x130>,
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<0x35200 0x200>,
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<0x35400 0x1dc>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "pcie_0_pipe_clk_src";
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "lane0";
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};
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pciephy_1: lane@36000 {
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...
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...
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};
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phy@88eb000 {
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compatible = "qcom,sdm845-qmp-usb3-uni-phy";
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reg = <0x88eb000 0x18c>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
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<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_USB3_SEC_CLKREF_CLK>,
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<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "com_aux";
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resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
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<&gcc GCC_USB3_PHY_SEC_BCR>;
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reset-names = "phy", "common";
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lane@88eb200 {
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reg = <0x88eb200 0x128>,
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<0x88eb400 0x1fc>,
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<0x88eb800 0x218>,
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<0x88eb600 0x70>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "usb3_uni_phy_pipe_clk_src";
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};
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};
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phy@1d87000 {
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compatible = "qcom,sdm845-qmp-ufs-phy";
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reg = <0x1d87000 0x18c>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock-names = "ref",
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"ref_aux";
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clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
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<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
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lanes@1d87400 {
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reg = <0x1d87400 0x108>,
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<0x1d87600 0x1e0>,
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<0x1d87c00 0x1dc>,
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<0x1d87800 0x108>,
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<0x1d87a00 0x1e0>;
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#phy-cells = <0>;
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};
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};
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