161 lines
4.9 KiB
C
161 lines
4.9 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_CACHEFLUSH_H
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#define _ASM_TILE_CACHEFLUSH_H
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#include <arch/chip.h>
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/* Keep includes the same across arches. */
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#include <linux/mm.h>
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#include <linux/cache.h>
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#include <arch/icache.h>
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/* Caches are physically-indexed and so don't need special treatment */
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#define flush_icache_page(vma, pg) do { } while (0)
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#define flush_icache_user_range(vma, pg, adr, len) do { } while (0)
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/* Flush the icache just on this cpu */
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extern void __flush_icache_range(unsigned long start, unsigned long end);
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/* Flush the entire icache on this cpu. */
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#define __flush_icache() __flush_icache_range(0, CHIP_L1I_CACHE_SIZE())
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#ifdef CONFIG_SMP
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/*
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* When the kernel writes to its own text we need to do an SMP
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* broadcast to make the L1I coherent everywhere. This includes
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* module load and single step.
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*/
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extern void flush_icache_range(unsigned long start, unsigned long end);
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#else
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#define flush_icache_range __flush_icache_range
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#endif
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/*
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* An update to an executable user page requires icache flushing.
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* We could carefully update only tiles that are running this process,
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* and rely on the fact that we flush the icache on every context
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* switch to avoid doing extra work here. But for now, I'll be
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* conservative and just do a global icache flush.
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*/
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static inline void copy_to_user_page(struct vm_area_struct *vma,
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struct page *page, unsigned long vaddr,
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void *dst, void *src, int len)
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{
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memcpy(dst, src, len);
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if (vma->vm_flags & VM_EXEC) {
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flush_icache_range((unsigned long) dst,
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(unsigned long) dst + len);
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}
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}
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy((dst), (src), (len))
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/* Flush a VA range; pads to L2 cacheline boundaries. */
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static inline void __flush_buffer(void *buffer, size_t size)
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{
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char *next = (char *)((long)buffer & -L2_CACHE_BYTES);
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char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size);
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while (next < finish) {
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__insn_flush(next);
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next += CHIP_FLUSH_STRIDE();
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}
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}
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/* Flush & invalidate a VA range; pads to L2 cacheline boundaries. */
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static inline void __finv_buffer(void *buffer, size_t size)
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{
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char *next = (char *)((long)buffer & -L2_CACHE_BYTES);
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char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size);
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while (next < finish) {
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__insn_finv(next);
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next += CHIP_FINV_STRIDE();
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}
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}
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/*
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* Flush a locally-homecached VA range and wait for the evicted
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* cachelines to hit memory.
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*/
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static inline void flush_buffer_local(void *buffer, size_t size)
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{
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__flush_buffer(buffer, size);
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mb_incoherent();
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}
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/*
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* Flush and invalidate a locally-homecached VA range and wait for the
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* evicted cachelines to hit memory.
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*/
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static inline void finv_buffer_local(void *buffer, size_t size)
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{
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__finv_buffer(buffer, size);
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mb_incoherent();
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}
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#ifdef __tilepro__
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/* Invalidate a VA range; pads to L2 cacheline boundaries. */
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static inline void __inv_buffer(void *buffer, size_t size)
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{
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char *next = (char *)((long)buffer & -L2_CACHE_BYTES);
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char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size);
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while (next < finish) {
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__insn_inv(next);
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next += CHIP_INV_STRIDE();
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}
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}
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/* Invalidate a VA range and wait for it to be complete. */
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static inline void inv_buffer(void *buffer, size_t size)
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{
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__inv_buffer(buffer, size);
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mb();
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}
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#endif
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/*
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* Flush and invalidate a VA range that is homed remotely, waiting
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* until the memory controller holds the flushed values. If "hfh" is
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* true, we will do a more expensive flush involving additional loads
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* to make sure we have touched all the possible home cpus of a buffer
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* that is homed with "hash for home".
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*/
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void finv_buffer_remote(void *buffer, size_t size, int hfh);
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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* it needs a way to flush as much of the CPU's caches as possible:
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*
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* TODO: fill this in!
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*/
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static inline void sched_cacheflush(void)
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{
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}
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#endif /* _ASM_TILE_CACHEFLUSH_H */
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