101 lines
2.9 KiB
C
101 lines
2.9 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_BARRIER_H
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#define _ASM_TILE_BARRIER_H
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <arch/chip.h>
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#include <arch/spr_def.h>
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#include <asm/timex.h>
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#define __sync() __insn_mf()
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#include <hv/syscall_public.h>
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/*
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* Issue an uncacheable load to each memory controller, then
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* wait until those loads have completed.
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*/
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static inline void __mb_incoherent(void)
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{
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long clobber_r10;
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asm volatile("swint2"
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: "=R10" (clobber_r10)
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: "R10" (HV_SYS_fence_incoherent)
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: "r0", "r1", "r2", "r3", "r4",
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"r5", "r6", "r7", "r8", "r9",
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"r11", "r12", "r13", "r14",
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"r15", "r16", "r17", "r18", "r19",
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"r20", "r21", "r22", "r23", "r24",
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"r25", "r26", "r27", "r28", "r29");
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}
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/* Fence to guarantee visibility of stores to incoherent memory. */
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static inline void
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mb_incoherent(void)
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{
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__insn_mf();
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{
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#if CHIP_HAS_TILE_WRITE_PENDING()
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const unsigned long WRITE_TIMEOUT_CYCLES = 400;
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unsigned long start = get_cycles_low();
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do {
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if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0)
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return;
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} while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES);
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#endif /* CHIP_HAS_TILE_WRITE_PENDING() */
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(void) __mb_incoherent();
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}
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}
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#define fast_wmb() __sync()
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#define fast_rmb() __sync()
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#define fast_mb() __sync()
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#define fast_iob() mb_incoherent()
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#define wmb() fast_wmb()
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#define rmb() fast_rmb()
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#define mb() fast_mb()
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#define iob() fast_iob()
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#ifndef __tilegx__ /* 32 bit */
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/*
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* We need to barrier before modifying the word, since the _atomic_xxx()
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* routines just tns the lock and then read/modify/write of the word.
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* But after the word is updated, the routine issues an "mf" before returning,
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* and since it's a function call, we don't even need a compiler barrier.
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*/
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#define __smp_mb__before_atomic() __smp_mb()
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#define __smp_mb__after_atomic() do { } while (0)
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#define smp_mb__after_atomic() __smp_mb__after_atomic()
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#else /* 64 bit */
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#define __smp_mb__before_atomic() __smp_mb()
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#define __smp_mb__after_atomic() __smp_mb()
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#endif
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/*
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* The TILE architecture does not do speculative reads; this ensures
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* that a control dependency also orders against loads and already provides
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* a LOAD->{LOAD,STORE} order and can forgo the additional RMB.
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*/
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#define smp_acquire__after_ctrl_dep() barrier()
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#include <asm-generic/barrier.h>
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_TILE_BARRIER_H */
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