245 lines
6.2 KiB
C
245 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Intel Corporation.
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*
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* Limitations:
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* - The hardware supports fixed period & configures only 2-wire mode.
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* - Supports normal polarity. Does not support changing polarity.
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* - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
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* keep track of running period.
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* - When duty cycle is changed, PWM output may be a mix of previous setting
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* and new setting for the first period. From second period, the output is
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* based on new setting.
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* - It is a dedicated PWM fan controller. There are no other consumers for
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* this PWM controller.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mod_devicetable.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#define LGM_PWM_FAN_CON0 0x0
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#define LGM_PWM_FAN_EN_EN BIT(0)
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#define LGM_PWM_FAN_EN_DIS 0x0
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#define LGM_PWM_FAN_EN_MSK BIT(0)
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#define LGM_PWM_FAN_MODE_2WIRE 0x0
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#define LGM_PWM_FAN_MODE_MSK BIT(1)
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#define LGM_PWM_FAN_DC_MSK GENMASK(23, 16)
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#define LGM_PWM_FAN_CON1 0x4
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#define LGM_PWM_FAN_MAX_RPM_MSK GENMASK(15, 0)
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#define LGM_PWM_MAX_RPM (BIT(16) - 1)
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#define LGM_PWM_DEFAULT_RPM 4000
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#define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
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#define LGM_PWM_DC_BITS 8
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#define LGM_PWM_PERIOD_2WIRE_NS (40 * NSEC_PER_MSEC)
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struct lgm_pwm_chip {
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struct pwm_chip chip;
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struct regmap *regmap;
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u32 period;
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};
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static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct lgm_pwm_chip, chip);
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}
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static int lgm_pwm_enable(struct pwm_chip *chip, bool enable)
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{
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struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
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struct regmap *regmap = pc->regmap;
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return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK,
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enable ? LGM_PWM_FAN_EN_EN : LGM_PWM_FAN_EN_DIS);
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}
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static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
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u32 duty_cycle, val;
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int ret;
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/* The hardware only supports normal polarity and fixed period. */
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if (state->polarity != PWM_POLARITY_NORMAL || state->period < pc->period)
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return -EINVAL;
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if (!state->enabled)
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return lgm_pwm_enable(chip, 0);
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duty_cycle = min_t(u64, state->duty_cycle, pc->period);
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val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period;
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ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_DC_MSK,
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FIELD_PREP(LGM_PWM_FAN_DC_MSK, val));
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if (ret)
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return ret;
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return lgm_pwm_enable(chip, 1);
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}
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static void lgm_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip);
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u32 duty, val;
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state->enabled = regmap_test_bits(pc->regmap, LGM_PWM_FAN_CON0,
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LGM_PWM_FAN_EN_EN);
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state->polarity = PWM_POLARITY_NORMAL;
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state->period = pc->period; /* fixed period */
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regmap_read(pc->regmap, LGM_PWM_FAN_CON0, &val);
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duty = FIELD_GET(LGM_PWM_FAN_DC_MSK, val);
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state->duty_cycle = DIV_ROUND_UP(duty * pc->period, LGM_PWM_MAX_DUTY_CYCLE);
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}
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static const struct pwm_ops lgm_pwm_ops = {
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.get_state = lgm_pwm_get_state,
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.apply = lgm_pwm_apply,
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.owner = THIS_MODULE,
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};
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static void lgm_pwm_init(struct lgm_pwm_chip *pc)
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{
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struct regmap *regmap = pc->regmap;
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u32 con0_val;
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con0_val = FIELD_PREP(LGM_PWM_FAN_MODE_MSK, LGM_PWM_FAN_MODE_2WIRE);
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pc->period = LGM_PWM_PERIOD_2WIRE_NS;
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regmap_update_bits(regmap, LGM_PWM_FAN_CON1, LGM_PWM_FAN_MAX_RPM_MSK,
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LGM_PWM_DEFAULT_RPM);
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regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_MODE_MSK,
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con0_val);
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}
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static const struct regmap_config lgm_pwm_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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};
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static void lgm_clk_release(void *data)
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{
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struct clk *clk = data;
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clk_disable_unprepare(clk);
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}
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static int lgm_clk_enable(struct device *dev, struct clk *clk)
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{
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int ret;
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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return devm_add_action_or_reset(dev, lgm_clk_release, clk);
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}
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static void lgm_reset_control_release(void *data)
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{
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struct reset_control *rst = data;
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reset_control_assert(rst);
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}
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static int lgm_reset_control_deassert(struct device *dev, struct reset_control *rst)
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{
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int ret;
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ret = reset_control_deassert(rst);
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if (ret)
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return ret;
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return devm_add_action_or_reset(dev, lgm_reset_control_release, rst);
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}
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static int lgm_pwm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct reset_control *rst;
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struct lgm_pwm_chip *pc;
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void __iomem *io_base;
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struct clk *clk;
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int ret;
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pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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platform_set_drvdata(pdev, pc);
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io_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(io_base))
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return PTR_ERR(io_base);
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pc->regmap = devm_regmap_init_mmio(dev, io_base, &lgm_pwm_regmap_config);
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if (IS_ERR(pc->regmap))
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return dev_err_probe(dev, PTR_ERR(pc->regmap),
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"failed to init register map\n");
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clk = devm_clk_get(dev, NULL);
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if (IS_ERR(clk))
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return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n");
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ret = lgm_clk_enable(dev, clk);
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if (ret)
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return dev_err_probe(dev, ret, "failed to enable clock\n");
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rst = devm_reset_control_get_exclusive(dev, NULL);
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if (IS_ERR(rst))
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return dev_err_probe(dev, PTR_ERR(rst),
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"failed to get reset control\n");
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ret = lgm_reset_control_deassert(dev, rst);
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if (ret)
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return dev_err_probe(dev, ret, "cannot deassert reset control\n");
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pc->chip.dev = dev;
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pc->chip.ops = &lgm_pwm_ops;
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pc->chip.npwm = 1;
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pc->chip.base = -1;
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lgm_pwm_init(pc);
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ret = pwmchip_add(&pc->chip);
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if (ret < 0)
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return dev_err_probe(dev, ret, "failed to add PWM chip\n");
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return 0;
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}
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static int lgm_pwm_remove(struct platform_device *pdev)
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{
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struct lgm_pwm_chip *pc = platform_get_drvdata(pdev);
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return pwmchip_remove(&pc->chip);
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}
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static const struct of_device_id lgm_pwm_of_match[] = {
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{ .compatible = "intel,lgm-pwm" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, lgm_pwm_of_match);
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static struct platform_driver lgm_pwm_driver = {
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.driver = {
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.name = "intel-pwm",
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.of_match_table = lgm_pwm_of_match,
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},
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.probe = lgm_pwm_probe,
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.remove = lgm_pwm_remove,
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};
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module_platform_driver(lgm_pwm_driver);
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MODULE_LICENSE("GPL v2");
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