51 lines
1.8 KiB
Plaintext
51 lines
1.8 KiB
Plaintext
HiSilicon Kirin SoCs PCIe host DT description
|
|
|
|
Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
|
|
It shares common functions with the PCIe DesignWare core driver and
|
|
inherits common properties defined in
|
|
Documentation/devicetree/bindings/pci/designware-pcie.txt.
|
|
|
|
Additional properties are described here:
|
|
|
|
Required properties
|
|
- compatible:
|
|
"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
|
|
- reg: Should contain rc_dbi, apb, phy, config registers location and length.
|
|
- reg-names: Must include the following entries:
|
|
"dbi": controller configuration registers;
|
|
"apb": apb Ctrl register defined by Kirin;
|
|
"phy": apb PHY register defined by Kirin;
|
|
"config": PCIe configuration space registers.
|
|
- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
|
|
|
|
Optional properties:
|
|
|
|
Example based on kirin960:
|
|
|
|
pcie@f4000000 {
|
|
compatible = "hisilicon,kirin-pcie";
|
|
reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
|
|
<0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
|
|
reg-names = "dbi","apb","phy", "config";
|
|
bus-range = <0x0 0x1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
|
|
num-lanes = <1>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
|
|
<0x0 0 0 2 &gic 0 0 0 283 4>,
|
|
<0x0 0 0 3 &gic 0 0 0 284 4>,
|
|
<0x0 0 0 4 &gic 0 0 0 285 4>;
|
|
clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
|
|
<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
|
|
<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
|
|
<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
|
|
<&crg_ctrl HI3660_ACLK_GATE_PCIE>;
|
|
clock-names = "pcie_phy_ref", "pcie_aux",
|
|
"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
|
|
reset-gpios = <&gpio11 1 0 >;
|
|
};
|