539 lines
12 KiB
C
539 lines
12 KiB
C
/*
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* drivers/net/ibm_newemac/phy.c
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*
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* Driver for PowerPC 4xx on-chip ethernet controller, PHY support.
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* Borrowed from sungem_phy.c, though I only kept the generic MII
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* driver for now.
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*
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* This file should be shared with other drivers or eventually
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* merged as the "low level" part of miilib
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*
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* Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
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* <benh@kernel.crashing.org>
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*
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* Based on the arch/ppc version of the driver:
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*
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* (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org)
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* (c) 2004-2005, Eugene Surovegin <ebs@ebshome.net>
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/netdevice.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/delay.h>
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#include "emac.h"
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#include "phy.h"
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static inline int phy_read(struct mii_phy *phy, int reg)
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{
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return phy->mdio_read(phy->dev, phy->address, reg);
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}
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static inline void phy_write(struct mii_phy *phy, int reg, int val)
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{
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phy->mdio_write(phy->dev, phy->address, reg, val);
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}
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static inline int gpcs_phy_read(struct mii_phy *phy, int reg)
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{
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return phy->mdio_read(phy->dev, phy->gpcs_address, reg);
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}
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static inline void gpcs_phy_write(struct mii_phy *phy, int reg, int val)
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{
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phy->mdio_write(phy->dev, phy->gpcs_address, reg, val);
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}
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int emac_mii_reset_phy(struct mii_phy *phy)
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{
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int val;
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int limit = 10000;
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val = phy_read(phy, MII_BMCR);
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val &= ~(BMCR_ISOLATE | BMCR_ANENABLE);
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val |= BMCR_RESET;
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phy_write(phy, MII_BMCR, val);
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udelay(300);
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while (--limit) {
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val = phy_read(phy, MII_BMCR);
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if (val >= 0 && (val & BMCR_RESET) == 0)
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break;
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udelay(10);
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}
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if ((val & BMCR_ISOLATE) && limit > 0)
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phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
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return limit <= 0;
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}
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int emac_mii_reset_gpcs(struct mii_phy *phy)
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{
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int val;
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int limit = 10000;
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val = gpcs_phy_read(phy, MII_BMCR);
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val &= ~(BMCR_ISOLATE | BMCR_ANENABLE);
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val |= BMCR_RESET;
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gpcs_phy_write(phy, MII_BMCR, val);
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udelay(300);
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while (--limit) {
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val = gpcs_phy_read(phy, MII_BMCR);
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if (val >= 0 && (val & BMCR_RESET) == 0)
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break;
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udelay(10);
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}
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if ((val & BMCR_ISOLATE) && limit > 0)
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gpcs_phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
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if (limit > 0 && phy->mode == PHY_MODE_SGMII) {
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/* Configure GPCS interface to recommended setting for SGMII */
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gpcs_phy_write(phy, 0x04, 0x8120); /* AsymPause, FDX */
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gpcs_phy_write(phy, 0x07, 0x2801); /* msg_pg, toggle */
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gpcs_phy_write(phy, 0x00, 0x0140); /* 1Gbps, FDX */
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}
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return limit <= 0;
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}
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static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
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{
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int ctl, adv;
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phy->autoneg = AUTONEG_ENABLE;
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phy->speed = SPEED_10;
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phy->duplex = DUPLEX_HALF;
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phy->pause = phy->asym_pause = 0;
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phy->advertising = advertise;
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ctl = phy_read(phy, MII_BMCR);
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if (ctl < 0)
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return ctl;
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ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
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/* First clear the PHY */
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phy_write(phy, MII_BMCR, ctl);
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/* Setup standard advertise */
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adv = phy_read(phy, MII_ADVERTISE);
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if (adv < 0)
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return adv;
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adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
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ADVERTISE_PAUSE_ASYM);
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if (advertise & ADVERTISED_10baseT_Half)
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adv |= ADVERTISE_10HALF;
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if (advertise & ADVERTISED_10baseT_Full)
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adv |= ADVERTISE_10FULL;
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if (advertise & ADVERTISED_100baseT_Half)
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adv |= ADVERTISE_100HALF;
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if (advertise & ADVERTISED_100baseT_Full)
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adv |= ADVERTISE_100FULL;
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if (advertise & ADVERTISED_Pause)
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adv |= ADVERTISE_PAUSE_CAP;
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if (advertise & ADVERTISED_Asym_Pause)
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adv |= ADVERTISE_PAUSE_ASYM;
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phy_write(phy, MII_ADVERTISE, adv);
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if (phy->features &
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(SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
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adv = phy_read(phy, MII_CTRL1000);
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if (adv < 0)
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return adv;
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adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
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if (advertise & ADVERTISED_1000baseT_Full)
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adv |= ADVERTISE_1000FULL;
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if (advertise & ADVERTISED_1000baseT_Half)
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adv |= ADVERTISE_1000HALF;
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phy_write(phy, MII_CTRL1000, adv);
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}
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/* Start/Restart aneg */
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ctl = phy_read(phy, MII_BMCR);
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ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
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phy_write(phy, MII_BMCR, ctl);
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return 0;
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}
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static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
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{
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int ctl;
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phy->autoneg = AUTONEG_DISABLE;
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phy->speed = speed;
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phy->duplex = fd;
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phy->pause = phy->asym_pause = 0;
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ctl = phy_read(phy, MII_BMCR);
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if (ctl < 0)
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return ctl;
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ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
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/* First clear the PHY */
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phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
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/* Select speed & duplex */
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switch (speed) {
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case SPEED_10:
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break;
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case SPEED_100:
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ctl |= BMCR_SPEED100;
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break;
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case SPEED_1000:
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ctl |= BMCR_SPEED1000;
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break;
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default:
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return -EINVAL;
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}
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if (fd == DUPLEX_FULL)
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ctl |= BMCR_FULLDPLX;
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phy_write(phy, MII_BMCR, ctl);
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return 0;
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}
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static int genmii_poll_link(struct mii_phy *phy)
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{
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int status;
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/* Clear latched value with dummy read */
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phy_read(phy, MII_BMSR);
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status = phy_read(phy, MII_BMSR);
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if (status < 0 || (status & BMSR_LSTATUS) == 0)
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return 0;
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if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE))
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return 0;
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return 1;
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}
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static int genmii_read_link(struct mii_phy *phy)
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{
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if (phy->autoneg == AUTONEG_ENABLE) {
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int glpa = 0;
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int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
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if (lpa < 0)
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return lpa;
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if (phy->features &
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(SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
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int adv = phy_read(phy, MII_CTRL1000);
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glpa = phy_read(phy, MII_STAT1000);
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if (glpa < 0 || adv < 0)
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return adv;
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glpa &= adv << 2;
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}
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phy->speed = SPEED_10;
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phy->duplex = DUPLEX_HALF;
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phy->pause = phy->asym_pause = 0;
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if (glpa & (LPA_1000FULL | LPA_1000HALF)) {
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phy->speed = SPEED_1000;
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if (glpa & LPA_1000FULL)
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phy->duplex = DUPLEX_FULL;
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} else if (lpa & (LPA_100FULL | LPA_100HALF)) {
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phy->speed = SPEED_100;
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if (lpa & LPA_100FULL)
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phy->duplex = DUPLEX_FULL;
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} else if (lpa & LPA_10FULL)
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phy->duplex = DUPLEX_FULL;
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if (phy->duplex == DUPLEX_FULL) {
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phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
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phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
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}
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} else {
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int bmcr = phy_read(phy, MII_BMCR);
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if (bmcr < 0)
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return bmcr;
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if (bmcr & BMCR_FULLDPLX)
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phy->duplex = DUPLEX_FULL;
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else
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phy->duplex = DUPLEX_HALF;
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if (bmcr & BMCR_SPEED1000)
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phy->speed = SPEED_1000;
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else if (bmcr & BMCR_SPEED100)
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phy->speed = SPEED_100;
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else
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phy->speed = SPEED_10;
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phy->pause = phy->asym_pause = 0;
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}
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return 0;
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}
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/* Generic implementation for most 10/100/1000 PHYs */
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static struct mii_phy_ops generic_phy_ops = {
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.setup_aneg = genmii_setup_aneg,
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.setup_forced = genmii_setup_forced,
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.poll_link = genmii_poll_link,
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.read_link = genmii_read_link
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};
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static struct mii_phy_def genmii_phy_def = {
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.phy_id = 0x00000000,
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.phy_id_mask = 0x00000000,
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.name = "Generic MII",
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.ops = &generic_phy_ops
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};
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/* CIS8201 */
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#define MII_CIS8201_10BTCSR 0x16
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#define TENBTCSR_ECHO_DISABLE 0x2000
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#define MII_CIS8201_EPCR 0x17
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#define EPCR_MODE_MASK 0x3000
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#define EPCR_GMII_MODE 0x0000
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#define EPCR_RGMII_MODE 0x1000
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#define EPCR_TBI_MODE 0x2000
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#define EPCR_RTBI_MODE 0x3000
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#define MII_CIS8201_ACSR 0x1c
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#define ACSR_PIN_PRIO_SELECT 0x0004
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static int cis8201_init(struct mii_phy *phy)
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{
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int epcr;
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epcr = phy_read(phy, MII_CIS8201_EPCR);
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if (epcr < 0)
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return epcr;
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epcr &= ~EPCR_MODE_MASK;
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switch (phy->mode) {
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case PHY_MODE_TBI:
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epcr |= EPCR_TBI_MODE;
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break;
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case PHY_MODE_RTBI:
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epcr |= EPCR_RTBI_MODE;
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break;
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case PHY_MODE_GMII:
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epcr |= EPCR_GMII_MODE;
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break;
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case PHY_MODE_RGMII:
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default:
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epcr |= EPCR_RGMII_MODE;
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}
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phy_write(phy, MII_CIS8201_EPCR, epcr);
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/* MII regs override strap pins */
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phy_write(phy, MII_CIS8201_ACSR,
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phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
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/* Disable TX_EN -> CRS echo mode, otherwise 10/HDX doesn't work */
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phy_write(phy, MII_CIS8201_10BTCSR,
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phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
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return 0;
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}
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static struct mii_phy_ops cis8201_phy_ops = {
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.init = cis8201_init,
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.setup_aneg = genmii_setup_aneg,
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.setup_forced = genmii_setup_forced,
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.poll_link = genmii_poll_link,
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.read_link = genmii_read_link
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};
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static struct mii_phy_def cis8201_phy_def = {
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.phy_id = 0x000fc410,
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.phy_id_mask = 0x000ffff0,
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.name = "CIS8201 Gigabit Ethernet",
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.ops = &cis8201_phy_ops
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};
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static struct mii_phy_def bcm5248_phy_def = {
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.phy_id = 0x0143bc00,
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.phy_id_mask = 0x0ffffff0,
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.name = "BCM5248 10/100 SMII Ethernet",
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.ops = &generic_phy_ops
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};
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static int m88e1111_init(struct mii_phy *phy)
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{
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pr_debug("%s: Marvell 88E1111 Ethernet\n", __func__);
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phy_write(phy, 0x14, 0x0ce3);
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phy_write(phy, 0x18, 0x4101);
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phy_write(phy, 0x09, 0x0e00);
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phy_write(phy, 0x04, 0x01e1);
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phy_write(phy, 0x00, 0x9140);
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phy_write(phy, 0x00, 0x1140);
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return 0;
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}
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static int m88e1112_init(struct mii_phy *phy)
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{
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/*
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* Marvell 88E1112 PHY needs to have the SGMII MAC
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* interace (page 2) properly configured to
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* communicate with the 460EX/GT GPCS interface.
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*/
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u16 reg_short;
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pr_debug("%s: Marvell 88E1112 Ethernet\n", __func__);
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/* Set access to Page 2 */
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phy_write(phy, 0x16, 0x0002);
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phy_write(phy, 0x00, 0x0040); /* 1Gbps */
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reg_short = (u16)(phy_read(phy, 0x1a));
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reg_short |= 0x8000; /* bypass Auto-Negotiation */
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phy_write(phy, 0x1a, reg_short);
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emac_mii_reset_phy(phy); /* reset MAC interface */
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/* Reset access to Page 0 */
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phy_write(phy, 0x16, 0x0000);
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return 0;
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}
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static int et1011c_init(struct mii_phy *phy)
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{
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u16 reg_short;
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reg_short = (u16)(phy_read(phy, 0x16));
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reg_short &= ~(0x7);
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reg_short |= 0x6; /* RGMII Trace Delay*/
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phy_write(phy, 0x16, reg_short);
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reg_short = (u16)(phy_read(phy, 0x17));
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reg_short &= ~(0x40);
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phy_write(phy, 0x17, reg_short);
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phy_write(phy, 0x1c, 0x74f0);
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return 0;
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}
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static struct mii_phy_ops et1011c_phy_ops = {
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.init = et1011c_init,
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.setup_aneg = genmii_setup_aneg,
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.setup_forced = genmii_setup_forced,
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.poll_link = genmii_poll_link,
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.read_link = genmii_read_link
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};
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static struct mii_phy_def et1011c_phy_def = {
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.phy_id = 0x0282f000,
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.phy_id_mask = 0x0fffff00,
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.name = "ET1011C Gigabit Ethernet",
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.ops = &et1011c_phy_ops
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};
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static struct mii_phy_ops m88e1111_phy_ops = {
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.init = m88e1111_init,
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.setup_aneg = genmii_setup_aneg,
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.setup_forced = genmii_setup_forced,
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.poll_link = genmii_poll_link,
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.read_link = genmii_read_link
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};
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static struct mii_phy_def m88e1111_phy_def = {
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.phy_id = 0x01410CC0,
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.phy_id_mask = 0x0ffffff0,
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.name = "Marvell 88E1111 Ethernet",
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.ops = &m88e1111_phy_ops,
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};
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static struct mii_phy_ops m88e1112_phy_ops = {
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.init = m88e1112_init,
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.setup_aneg = genmii_setup_aneg,
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.setup_forced = genmii_setup_forced,
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.poll_link = genmii_poll_link,
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.read_link = genmii_read_link
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};
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static struct mii_phy_def m88e1112_phy_def = {
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.phy_id = 0x01410C90,
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.phy_id_mask = 0x0ffffff0,
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.name = "Marvell 88E1112 Ethernet",
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.ops = &m88e1112_phy_ops,
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};
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static struct mii_phy_def *mii_phy_table[] = {
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&et1011c_phy_def,
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&cis8201_phy_def,
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&bcm5248_phy_def,
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&m88e1111_phy_def,
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&m88e1112_phy_def,
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&genmii_phy_def,
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NULL
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};
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int emac_mii_phy_probe(struct mii_phy *phy, int address)
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{
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struct mii_phy_def *def;
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int i;
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u32 id;
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phy->autoneg = AUTONEG_DISABLE;
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phy->advertising = 0;
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phy->address = address;
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phy->speed = SPEED_10;
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phy->duplex = DUPLEX_HALF;
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phy->pause = phy->asym_pause = 0;
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/* Take PHY out of isolate mode and reset it. */
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if (emac_mii_reset_phy(phy))
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return -ENODEV;
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/* Read ID and find matching entry */
|
|
id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2);
|
|
for (i = 0; (def = mii_phy_table[i]) != NULL; i++)
|
|
if ((id & def->phy_id_mask) == def->phy_id)
|
|
break;
|
|
/* Should never be NULL (we have a generic entry), but... */
|
|
if (!def)
|
|
return -ENODEV;
|
|
|
|
phy->def = def;
|
|
|
|
/* Determine PHY features if needed */
|
|
phy->features = def->features;
|
|
if (!phy->features) {
|
|
u16 bmsr = phy_read(phy, MII_BMSR);
|
|
if (bmsr & BMSR_ANEGCAPABLE)
|
|
phy->features |= SUPPORTED_Autoneg;
|
|
if (bmsr & BMSR_10HALF)
|
|
phy->features |= SUPPORTED_10baseT_Half;
|
|
if (bmsr & BMSR_10FULL)
|
|
phy->features |= SUPPORTED_10baseT_Full;
|
|
if (bmsr & BMSR_100HALF)
|
|
phy->features |= SUPPORTED_100baseT_Half;
|
|
if (bmsr & BMSR_100FULL)
|
|
phy->features |= SUPPORTED_100baseT_Full;
|
|
if (bmsr & BMSR_ESTATEN) {
|
|
u16 esr = phy_read(phy, MII_ESTATUS);
|
|
if (esr & ESTATUS_1000_TFULL)
|
|
phy->features |= SUPPORTED_1000baseT_Full;
|
|
if (esr & ESTATUS_1000_THALF)
|
|
phy->features |= SUPPORTED_1000baseT_Half;
|
|
}
|
|
phy->features |= SUPPORTED_MII;
|
|
}
|
|
|
|
/* Setup default advertising */
|
|
phy->advertising = phy->features;
|
|
|
|
return 0;
|
|
}
|
|
|
|
MODULE_LICENSE("GPL");
|