088e88be5a
Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs. The IP block contains settings for the PHY and a PLL. The PLL mode is configurable through a dedicated #phy-cell in .dts. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> |
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bindings | ||
booting-without-of.txt | ||
changesets.txt | ||
dynamic-resolution-notes.txt | ||
of_unittest.txt | ||
overlay-notes.txt | ||
usage-model.txt | ||
writing-schema.md |