545 lines
13 KiB
C
545 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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// Copyright (C) IBM Corporation 2018
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// FSI master driver for AST2600
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/fsi.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/iopoll.h>
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#include "fsi-master.h"
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struct fsi_master_aspeed {
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struct fsi_master master;
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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};
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#define to_fsi_master_aspeed(m) \
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container_of(m, struct fsi_master_aspeed, master)
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/* Control register (size 0x400) */
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static const u32 ctrl_base = 0x80000000;
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static const u32 fsi_base = 0xa0000000;
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#define OPB_FSI_VER 0x00
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#define OPB_TRIGGER 0x04
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#define OPB_CTRL_BASE 0x08
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#define OPB_FSI_BASE 0x0c
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#define OPB_CLK_SYNC 0x3c
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#define OPB_IRQ_CLEAR 0x40
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#define OPB_IRQ_MASK 0x44
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#define OPB_IRQ_STATUS 0x48
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#define OPB0_SELECT 0x10
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#define OPB0_RW 0x14
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#define OPB0_XFER_SIZE 0x18
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#define OPB0_FSI_ADDR 0x1c
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#define OPB0_FSI_DATA_W 0x20
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#define OPB0_STATUS 0x80
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#define OPB0_FSI_DATA_R 0x84
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#define OPB0_WRITE_ORDER1 0x4c
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#define OPB0_WRITE_ORDER2 0x50
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#define OPB1_WRITE_ORDER1 0x54
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#define OPB1_WRITE_ORDER2 0x58
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#define OPB0_READ_ORDER1 0x5c
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#define OPB1_READ_ORDER2 0x60
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#define OPB_RETRY_COUNTER 0x64
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/* OPBn_STATUS */
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#define STATUS_HALFWORD_ACK BIT(0)
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#define STATUS_FULLWORD_ACK BIT(1)
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#define STATUS_ERR_ACK BIT(2)
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#define STATUS_RETRY BIT(3)
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#define STATUS_TIMEOUT BIT(4)
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/* OPB_IRQ_MASK */
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#define OPB1_XFER_ACK_EN BIT(17)
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#define OPB0_XFER_ACK_EN BIT(16)
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/* OPB_RW */
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#define CMD_READ BIT(0)
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#define CMD_WRITE 0
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/* OPBx_XFER_SIZE */
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#define XFER_FULLWORD (BIT(1) | BIT(0))
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#define XFER_HALFWORD (BIT(0))
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#define XFER_BYTE (0)
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#define CREATE_TRACE_POINTS
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#include <trace/events/fsi_master_aspeed.h>
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#define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */
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#define DEFAULT_DIVISOR 14
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#define OPB_POLL_TIMEOUT 10000
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static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr,
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u32 val, u32 transfer_size)
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{
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void __iomem *base = aspeed->base;
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u32 reg, status;
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int ret;
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writel(CMD_WRITE, base + OPB0_RW);
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writel(transfer_size, base + OPB0_XFER_SIZE);
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writel(addr, base + OPB0_FSI_ADDR);
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writel(val, base + OPB0_FSI_DATA_W);
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writel(0x1, base + OPB_IRQ_CLEAR);
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writel(0x1, base + OPB_TRIGGER);
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ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg,
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(reg & OPB0_XFER_ACK_EN) != 0,
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0, OPB_POLL_TIMEOUT);
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status = readl(base + OPB0_STATUS);
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trace_fsi_master_aspeed_opb_write(addr, val, transfer_size, status, reg);
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/* Return error when poll timed out */
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if (ret)
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return ret;
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/* Command failed, master will reset */
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if (status & STATUS_ERR_ACK)
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return -EIO;
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return 0;
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}
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static int opb_writeb(struct fsi_master_aspeed *aspeed, u32 addr, u8 val)
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{
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return __opb_write(aspeed, addr, val, XFER_BYTE);
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}
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static int opb_writew(struct fsi_master_aspeed *aspeed, u32 addr, __be16 val)
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{
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return __opb_write(aspeed, addr, (__force u16)val, XFER_HALFWORD);
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}
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static int opb_writel(struct fsi_master_aspeed *aspeed, u32 addr, __be32 val)
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{
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return __opb_write(aspeed, addr, (__force u32)val, XFER_FULLWORD);
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}
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static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr,
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u32 transfer_size, void *out)
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{
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void __iomem *base = aspeed->base;
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u32 result, reg;
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int status, ret;
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writel(CMD_READ, base + OPB0_RW);
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writel(transfer_size, base + OPB0_XFER_SIZE);
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writel(addr, base + OPB0_FSI_ADDR);
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writel(0x1, base + OPB_IRQ_CLEAR);
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writel(0x1, base + OPB_TRIGGER);
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ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg,
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(reg & OPB0_XFER_ACK_EN) != 0,
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0, OPB_POLL_TIMEOUT);
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status = readl(base + OPB0_STATUS);
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result = readl(base + OPB0_FSI_DATA_R);
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trace_fsi_master_aspeed_opb_read(addr, transfer_size, result,
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readl(base + OPB0_STATUS),
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reg);
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/* Return error when poll timed out */
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if (ret)
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return ret;
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/* Command failed, master will reset */
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if (status & STATUS_ERR_ACK)
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return -EIO;
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if (out) {
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switch (transfer_size) {
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case XFER_BYTE:
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*(u8 *)out = result;
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break;
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case XFER_HALFWORD:
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*(u16 *)out = result;
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break;
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case XFER_FULLWORD:
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*(u32 *)out = result;
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break;
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default:
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return -EINVAL;
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}
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}
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return 0;
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}
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static int opb_readl(struct fsi_master_aspeed *aspeed, uint32_t addr, __be32 *out)
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{
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return __opb_read(aspeed, addr, XFER_FULLWORD, out);
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}
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static int opb_readw(struct fsi_master_aspeed *aspeed, uint32_t addr, __be16 *out)
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{
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return __opb_read(aspeed, addr, XFER_HALFWORD, (void *)out);
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}
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static int opb_readb(struct fsi_master_aspeed *aspeed, uint32_t addr, u8 *out)
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{
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return __opb_read(aspeed, addr, XFER_BYTE, (void *)out);
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}
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static int check_errors(struct fsi_master_aspeed *aspeed, int err)
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{
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int ret;
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if (trace_fsi_master_aspeed_opb_error_enabled()) {
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__be32 mresp0, mstap0, mesrb0;
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opb_readl(aspeed, ctrl_base + FSI_MRESP0, &mresp0);
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opb_readl(aspeed, ctrl_base + FSI_MSTAP0, &mstap0);
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opb_readl(aspeed, ctrl_base + FSI_MESRB0, &mesrb0);
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trace_fsi_master_aspeed_opb_error(
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be32_to_cpu(mresp0),
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be32_to_cpu(mstap0),
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be32_to_cpu(mesrb0));
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}
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if (err == -EIO) {
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/* Check MAEB (0x70) ? */
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/* Then clear errors in master */
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ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0,
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cpu_to_be32(FSI_MRESP_RST_ALL_MASTER));
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if (ret) {
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/* TODO: log? return different code? */
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return ret;
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}
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/* TODO: confirm that 0x70 was okay */
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}
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/* This will pass through timeout errors */
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return err;
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}
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static int aspeed_master_read(struct fsi_master *master, int link,
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uint8_t id, uint32_t addr, void *val, size_t size)
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{
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struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master);
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int ret;
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if (id != 0)
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return -EINVAL;
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addr += link * FSI_HUB_LINK_SIZE;
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switch (size) {
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case 1:
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ret = opb_readb(aspeed, fsi_base + addr, val);
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break;
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case 2:
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ret = opb_readw(aspeed, fsi_base + addr, val);
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break;
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case 4:
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ret = opb_readl(aspeed, fsi_base + addr, val);
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break;
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default:
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return -EINVAL;
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}
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ret = check_errors(aspeed, ret);
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if (ret)
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return ret;
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return 0;
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}
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static int aspeed_master_write(struct fsi_master *master, int link,
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uint8_t id, uint32_t addr, const void *val, size_t size)
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{
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struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master);
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int ret;
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if (id != 0)
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return -EINVAL;
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addr += link * FSI_HUB_LINK_SIZE;
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switch (size) {
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case 1:
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ret = opb_writeb(aspeed, fsi_base + addr, *(u8 *)val);
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break;
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case 2:
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ret = opb_writew(aspeed, fsi_base + addr, *(__be16 *)val);
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break;
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case 4:
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ret = opb_writel(aspeed, fsi_base + addr, *(__be32 *)val);
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break;
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default:
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return -EINVAL;
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}
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ret = check_errors(aspeed, ret);
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if (ret)
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return ret;
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return 0;
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}
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static int aspeed_master_link_enable(struct fsi_master *master, int link)
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{
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struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master);
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int idx, bit, ret;
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__be32 reg, result;
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idx = link / 32;
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bit = link % 32;
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reg = cpu_to_be32(0x80000000 >> bit);
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ret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg);
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if (ret)
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return ret;
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mdelay(FSI_LINK_ENABLE_SETUP_TIME);
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ret = opb_readl(aspeed, ctrl_base + FSI_MENP0 + (4 * idx), &result);
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if (ret)
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return ret;
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if (result != reg) {
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dev_err(aspeed->dev, "%s failed: %08x\n", __func__, result);
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return -EIO;
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}
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return 0;
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}
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static int aspeed_master_term(struct fsi_master *master, int link, uint8_t id)
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{
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uint32_t addr;
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__be32 cmd;
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addr = 0x4;
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cmd = cpu_to_be32(0xecc00000);
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return aspeed_master_write(master, link, id, addr, &cmd, 4);
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}
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static int aspeed_master_break(struct fsi_master *master, int link)
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{
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uint32_t addr;
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__be32 cmd;
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addr = 0x0;
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cmd = cpu_to_be32(0xc0de0000);
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return aspeed_master_write(master, link, 0, addr, &cmd, 4);
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}
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static void aspeed_master_release(struct device *dev)
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{
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struct fsi_master_aspeed *aspeed =
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to_fsi_master_aspeed(dev_to_fsi_master(dev));
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kfree(aspeed);
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}
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/* mmode encoders */
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static inline u32 fsi_mmode_crs0(u32 x)
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{
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return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT;
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}
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static inline u32 fsi_mmode_crs1(u32 x)
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{
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return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT;
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}
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static int aspeed_master_init(struct fsi_master_aspeed *aspeed)
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{
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__be32 reg;
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reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK
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| FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);
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opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);
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/* Initialize the MFSI (hub master) engine */
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reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK
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| FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);
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opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);
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reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM);
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opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg);
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reg = cpu_to_be32(FSI_MMODE_ECRC | FSI_MMODE_EPC | FSI_MMODE_RELA
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| fsi_mmode_crs0(DEFAULT_DIVISOR)
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| fsi_mmode_crs1(DEFAULT_DIVISOR)
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| FSI_MMODE_P8_TO_LSB);
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opb_writel(aspeed, ctrl_base + FSI_MMODE, reg);
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reg = cpu_to_be32(0xffff0000);
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opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg);
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reg = cpu_to_be32(~0);
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opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg);
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/* Leave enabled long enough for master logic to set up */
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mdelay(FSI_LINK_ENABLE_SETUP_TIME);
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opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg);
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opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL);
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reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK);
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opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);
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opb_readl(aspeed, ctrl_base + FSI_MLEVP0, NULL);
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/* Reset the master bridge */
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reg = cpu_to_be32(FSI_MRESB_RST_GEN);
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opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);
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reg = cpu_to_be32(FSI_MRESB_RST_ERR);
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opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);
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return 0;
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}
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static int fsi_master_aspeed_probe(struct platform_device *pdev)
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{
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struct fsi_master_aspeed *aspeed;
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struct resource *res;
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int rc, links, reg;
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__be32 raw;
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aspeed = devm_kzalloc(&pdev->dev, sizeof(*aspeed), GFP_KERNEL);
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if (!aspeed)
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return -ENOMEM;
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aspeed->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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aspeed->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(aspeed->base))
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return PTR_ERR(aspeed->base);
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aspeed->clk = devm_clk_get(aspeed->dev, NULL);
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if (IS_ERR(aspeed->clk)) {
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dev_err(aspeed->dev, "couldn't get clock\n");
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return PTR_ERR(aspeed->clk);
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}
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rc = clk_prepare_enable(aspeed->clk);
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if (rc) {
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dev_err(aspeed->dev, "couldn't enable clock\n");
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return rc;
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}
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writel(0x1, aspeed->base + OPB_CLK_SYNC);
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writel(OPB1_XFER_ACK_EN | OPB0_XFER_ACK_EN,
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aspeed->base + OPB_IRQ_MASK);
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/* TODO: determine an appropriate value */
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writel(0x10, aspeed->base + OPB_RETRY_COUNTER);
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writel(ctrl_base, aspeed->base + OPB_CTRL_BASE);
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writel(fsi_base, aspeed->base + OPB_FSI_BASE);
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/* Set read data order */
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writel(0x00030b1b, aspeed->base + OPB0_READ_ORDER1);
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/* Set write data order */
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writel(0x0011101b, aspeed->base + OPB0_WRITE_ORDER1);
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writel(0x0c330f3f, aspeed->base + OPB0_WRITE_ORDER2);
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/*
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* Select OPB0 for all operations.
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* Will need to be reworked when enabling DMA or anything that uses
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* OPB1.
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*/
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writel(0x1, aspeed->base + OPB0_SELECT);
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rc = opb_readl(aspeed, ctrl_base + FSI_MVER, &raw);
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if (rc) {
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dev_err(&pdev->dev, "failed to read hub version\n");
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return rc;
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}
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reg = be32_to_cpu(raw);
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links = (reg >> 8) & 0xff;
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dev_info(&pdev->dev, "hub version %08x (%d links)\n", reg, links);
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aspeed->master.dev.parent = &pdev->dev;
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aspeed->master.dev.release = aspeed_master_release;
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aspeed->master.dev.of_node = of_node_get(dev_of_node(&pdev->dev));
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|
aspeed->master.n_links = links;
|
|
aspeed->master.read = aspeed_master_read;
|
|
aspeed->master.write = aspeed_master_write;
|
|
aspeed->master.send_break = aspeed_master_break;
|
|
aspeed->master.term = aspeed_master_term;
|
|
aspeed->master.link_enable = aspeed_master_link_enable;
|
|
|
|
dev_set_drvdata(&pdev->dev, aspeed);
|
|
|
|
aspeed_master_init(aspeed);
|
|
|
|
rc = fsi_master_register(&aspeed->master);
|
|
if (rc)
|
|
goto err_release;
|
|
|
|
/* At this point, fsi_master_register performs the device_initialize(),
|
|
* and holds the sole reference on master.dev. This means the device
|
|
* will be freed (via ->release) during any subsequent call to
|
|
* fsi_master_unregister. We add our own reference to it here, so we
|
|
* can perform cleanup (in _remove()) without it being freed before
|
|
* we're ready.
|
|
*/
|
|
get_device(&aspeed->master.dev);
|
|
return 0;
|
|
|
|
err_release:
|
|
clk_disable_unprepare(aspeed->clk);
|
|
return rc;
|
|
}
|
|
|
|
static int fsi_master_aspeed_remove(struct platform_device *pdev)
|
|
{
|
|
struct fsi_master_aspeed *aspeed = platform_get_drvdata(pdev);
|
|
|
|
fsi_master_unregister(&aspeed->master);
|
|
clk_disable_unprepare(aspeed->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id fsi_master_aspeed_match[] = {
|
|
{ .compatible = "aspeed,ast2600-fsi-master" },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver fsi_master_aspeed_driver = {
|
|
.driver = {
|
|
.name = "fsi-master-aspeed",
|
|
.of_match_table = fsi_master_aspeed_match,
|
|
},
|
|
.probe = fsi_master_aspeed_probe,
|
|
.remove = fsi_master_aspeed_remove,
|
|
};
|
|
|
|
module_platform_driver(fsi_master_aspeed_driver);
|
|
MODULE_LICENSE("GPL");
|