2113 lines
51 KiB
C
2113 lines
51 KiB
C
/*
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* Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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* Leo Duran <leo.duran@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#include <linux/interrupt.h>
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#include <linux/msi.h>
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#include <linux/amd-iommu.h>
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#include <linux/export.h>
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#include <acpi/acpi.h>
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#include <asm/pci-direct.h>
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#include <asm/iommu.h>
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#include <asm/gart.h>
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#include <asm/x86_init.h>
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#include <asm/iommu_table.h>
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#include <asm/io_apic.h>
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#include <asm/irq_remapping.h>
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#include "amd_iommu_proto.h"
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#include "amd_iommu_types.h"
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#include "irq_remapping.h"
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/*
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* definitions for the ACPI scanning code
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*/
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#define IVRS_HEADER_LENGTH 48
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#define ACPI_IVHD_TYPE 0x10
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#define ACPI_IVMD_TYPE_ALL 0x20
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#define ACPI_IVMD_TYPE 0x21
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#define ACPI_IVMD_TYPE_RANGE 0x22
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#define IVHD_DEV_ALL 0x01
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#define IVHD_DEV_SELECT 0x02
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#define IVHD_DEV_SELECT_RANGE_START 0x03
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#define IVHD_DEV_RANGE_END 0x04
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#define IVHD_DEV_ALIAS 0x42
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#define IVHD_DEV_ALIAS_RANGE 0x43
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#define IVHD_DEV_EXT_SELECT 0x46
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#define IVHD_DEV_EXT_SELECT_RANGE 0x47
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#define IVHD_DEV_SPECIAL 0x48
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#define IVHD_SPECIAL_IOAPIC 1
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#define IVHD_SPECIAL_HPET 2
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#define IVHD_FLAG_HT_TUN_EN_MASK 0x01
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#define IVHD_FLAG_PASSPW_EN_MASK 0x02
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#define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
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#define IVHD_FLAG_ISOC_EN_MASK 0x08
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#define IVMD_FLAG_EXCL_RANGE 0x08
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#define IVMD_FLAG_UNITY_MAP 0x01
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#define ACPI_DEVFLAG_INITPASS 0x01
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#define ACPI_DEVFLAG_EXTINT 0x02
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#define ACPI_DEVFLAG_NMI 0x04
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#define ACPI_DEVFLAG_SYSMGT1 0x10
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#define ACPI_DEVFLAG_SYSMGT2 0x20
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#define ACPI_DEVFLAG_LINT0 0x40
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#define ACPI_DEVFLAG_LINT1 0x80
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#define ACPI_DEVFLAG_ATSDIS 0x10000000
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/*
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* ACPI table definitions
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*
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* These data structures are laid over the table to parse the important values
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* out of it.
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*/
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/*
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* structure describing one IOMMU in the ACPI table. Typically followed by one
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* or more ivhd_entrys.
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*/
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struct ivhd_header {
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u8 type;
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u8 flags;
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u16 length;
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u16 devid;
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u16 cap_ptr;
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u64 mmio_phys;
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u16 pci_seg;
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u16 info;
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u32 reserved;
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} __attribute__((packed));
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/*
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* A device entry describing which devices a specific IOMMU translates and
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* which requestor ids they use.
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*/
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struct ivhd_entry {
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u8 type;
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u16 devid;
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u8 flags;
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u32 ext;
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} __attribute__((packed));
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/*
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* An AMD IOMMU memory definition structure. It defines things like exclusion
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* ranges for devices and regions that should be unity mapped.
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*/
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struct ivmd_header {
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u8 type;
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u8 flags;
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u16 length;
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u16 devid;
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u16 aux;
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u64 resv;
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u64 range_start;
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u64 range_length;
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} __attribute__((packed));
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bool amd_iommu_dump;
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bool amd_iommu_irq_remap __read_mostly;
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static bool amd_iommu_detected;
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static bool __initdata amd_iommu_disabled;
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u16 amd_iommu_last_bdf; /* largest PCI device id we have
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to handle */
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LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
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we find in ACPI */
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u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */
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LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
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system */
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/* Array to assign indices to IOMMUs*/
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struct amd_iommu *amd_iommus[MAX_IOMMUS];
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int amd_iommus_present;
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/* IOMMUs have a non-present cache? */
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bool amd_iommu_np_cache __read_mostly;
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bool amd_iommu_iotlb_sup __read_mostly = true;
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u32 amd_iommu_max_pasids __read_mostly = ~0;
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bool amd_iommu_v2_present __read_mostly;
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bool amd_iommu_force_isolation __read_mostly;
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/*
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* List of protection domains - used during resume
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*/
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LIST_HEAD(amd_iommu_pd_list);
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spinlock_t amd_iommu_pd_lock;
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/*
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* Pointer to the device table which is shared by all AMD IOMMUs
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* it is indexed by the PCI device id or the HT unit id and contains
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* information about the domain the device belongs to as well as the
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* page table root pointer.
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*/
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struct dev_table_entry *amd_iommu_dev_table;
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/*
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* The alias table is a driver specific data structure which contains the
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* mappings of the PCI device ids to the actual requestor ids on the IOMMU.
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* More than one device can share the same requestor id.
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*/
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u16 *amd_iommu_alias_table;
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/*
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* The rlookup table is used to find the IOMMU which is responsible
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* for a specific device. It is also indexed by the PCI device id.
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*/
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struct amd_iommu **amd_iommu_rlookup_table;
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/*
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* This table is used to find the irq remapping table for a given device id
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* quickly.
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*/
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struct irq_remap_table **irq_lookup_table;
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/*
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* AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
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* to know which ones are already in use.
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*/
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unsigned long *amd_iommu_pd_alloc_bitmap;
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static u32 dev_table_size; /* size of the device table */
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static u32 alias_table_size; /* size of the alias table */
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static u32 rlookup_table_size; /* size if the rlookup table */
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enum iommu_init_state {
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IOMMU_START_STATE,
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IOMMU_IVRS_DETECTED,
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IOMMU_ACPI_FINISHED,
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IOMMU_ENABLED,
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IOMMU_PCI_INIT,
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IOMMU_INTERRUPTS_EN,
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IOMMU_DMA_OPS,
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IOMMU_INITIALIZED,
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IOMMU_NOT_FOUND,
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IOMMU_INIT_ERROR,
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};
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static enum iommu_init_state init_state = IOMMU_START_STATE;
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static int amd_iommu_enable_interrupts(void);
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static int __init iommu_go_to_state(enum iommu_init_state state);
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static inline void update_last_devid(u16 devid)
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{
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if (devid > amd_iommu_last_bdf)
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amd_iommu_last_bdf = devid;
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}
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static inline unsigned long tbl_size(int entry_size)
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{
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unsigned shift = PAGE_SHIFT +
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get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
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return 1UL << shift;
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}
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/* Access to l1 and l2 indexed register spaces */
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static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
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{
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u32 val;
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pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
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pci_read_config_dword(iommu->dev, 0xfc, &val);
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return val;
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}
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static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
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{
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pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
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pci_write_config_dword(iommu->dev, 0xfc, val);
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pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
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}
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static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
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{
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u32 val;
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pci_write_config_dword(iommu->dev, 0xf0, address);
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pci_read_config_dword(iommu->dev, 0xf4, &val);
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return val;
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}
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static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
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{
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pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
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pci_write_config_dword(iommu->dev, 0xf4, val);
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}
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/****************************************************************************
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*
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* AMD IOMMU MMIO register space handling functions
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*
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* These functions are used to program the IOMMU device registers in
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* MMIO space required for that driver.
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*
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****************************************************************************/
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/*
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* This function set the exclusion range in the IOMMU. DMA accesses to the
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* exclusion range are passed through untranslated
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*/
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static void iommu_set_exclusion_range(struct amd_iommu *iommu)
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{
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u64 start = iommu->exclusion_start & PAGE_MASK;
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u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
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u64 entry;
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if (!iommu->exclusion_start)
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return;
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entry = start | MMIO_EXCL_ENABLE_MASK;
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memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
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&entry, sizeof(entry));
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entry = limit;
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memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
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&entry, sizeof(entry));
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}
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/* Programs the physical address of the device table into the IOMMU hardware */
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static void iommu_set_device_table(struct amd_iommu *iommu)
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{
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u64 entry;
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BUG_ON(iommu->mmio_base == NULL);
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entry = virt_to_phys(amd_iommu_dev_table);
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entry |= (dev_table_size >> 12) - 1;
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memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
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&entry, sizeof(entry));
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}
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/* Generic functions to enable/disable certain features of the IOMMU. */
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static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
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{
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u32 ctrl;
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ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
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ctrl |= (1 << bit);
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writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
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}
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static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
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{
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u32 ctrl;
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ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
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ctrl &= ~(1 << bit);
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writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
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}
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static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
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{
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u32 ctrl;
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ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
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ctrl &= ~CTRL_INV_TO_MASK;
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ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
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writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
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}
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/* Function to enable the hardware */
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static void iommu_enable(struct amd_iommu *iommu)
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{
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iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
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}
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static void iommu_disable(struct amd_iommu *iommu)
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{
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/* Disable command buffer */
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iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
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/* Disable event logging and event interrupts */
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iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
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iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
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/* Disable IOMMU hardware itself */
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iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
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}
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/*
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* mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
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* the system has one.
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*/
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static u8 __iomem * __init iommu_map_mmio_space(u64 address)
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{
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if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
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pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
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address);
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pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
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return NULL;
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}
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return (u8 __iomem *)ioremap_nocache(address, MMIO_REGION_LENGTH);
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}
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static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
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{
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if (iommu->mmio_base)
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iounmap(iommu->mmio_base);
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release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
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}
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/****************************************************************************
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*
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* The functions below belong to the first pass of AMD IOMMU ACPI table
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* parsing. In this pass we try to find out the highest device id this
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* code has to handle. Upon this information the size of the shared data
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* structures is determined later.
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*
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****************************************************************************/
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/*
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* This function calculates the length of a given IVHD entry
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*/
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static inline int ivhd_entry_length(u8 *ivhd)
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{
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return 0x04 << (*ivhd >> 6);
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}
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/*
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* This function reads the last device id the IOMMU has to handle from the PCI
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* capability header for this IOMMU
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*/
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static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
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{
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u32 cap;
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cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
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update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
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return 0;
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}
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/*
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* After reading the highest device id from the IOMMU PCI capability header
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* this function looks if there is a higher device id defined in the ACPI table
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*/
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static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
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{
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u8 *p = (void *)h, *end = (void *)h;
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struct ivhd_entry *dev;
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p += sizeof(*h);
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end += h->length;
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find_last_devid_on_pci(PCI_BUS(h->devid),
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PCI_SLOT(h->devid),
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PCI_FUNC(h->devid),
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h->cap_ptr);
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while (p < end) {
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dev = (struct ivhd_entry *)p;
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switch (dev->type) {
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case IVHD_DEV_SELECT:
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case IVHD_DEV_RANGE_END:
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case IVHD_DEV_ALIAS:
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case IVHD_DEV_EXT_SELECT:
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/* all the above subfield types refer to device ids */
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update_last_devid(dev->devid);
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break;
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default:
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break;
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}
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p += ivhd_entry_length(p);
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}
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WARN_ON(p != end);
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return 0;
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}
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/*
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* Iterate over all IVHD entries in the ACPI table and find the highest device
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* id which we need to handle. This is the first of three functions which parse
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* the ACPI table. So we check the checksum here.
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*/
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static int __init find_last_devid_acpi(struct acpi_table_header *table)
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{
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int i;
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u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
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struct ivhd_header *h;
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/*
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* Validate checksum here so we don't need to do it when
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* we actually parse the table
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*/
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for (i = 0; i < table->length; ++i)
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checksum += p[i];
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if (checksum != 0)
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/* ACPI table corrupt */
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return -ENODEV;
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p += IVRS_HEADER_LENGTH;
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end += table->length;
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while (p < end) {
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h = (struct ivhd_header *)p;
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switch (h->type) {
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case ACPI_IVHD_TYPE:
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find_last_devid_from_ivhd(h);
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break;
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default:
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break;
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}
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p += h->length;
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}
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WARN_ON(p != end);
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return 0;
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}
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|
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/****************************************************************************
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*
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* The following functions belong to the code path which parses the ACPI table
|
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* the second time. In this ACPI parsing iteration we allocate IOMMU specific
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* data structures, initialize the device/alias/rlookup table and also
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* basically initialize the hardware.
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*
|
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****************************************************************************/
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/*
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* Allocates the command buffer. This buffer is per AMD IOMMU. We can
|
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* write commands to that buffer later and the IOMMU will execute them
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* asynchronously
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*/
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static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
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{
|
|
u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
|
|
get_order(CMD_BUFFER_SIZE));
|
|
|
|
if (cmd_buf == NULL)
|
|
return NULL;
|
|
|
|
iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
|
|
|
|
return cmd_buf;
|
|
}
|
|
|
|
/*
|
|
* This function resets the command buffer if the IOMMU stopped fetching
|
|
* commands from it.
|
|
*/
|
|
void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
|
|
{
|
|
iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
|
|
|
|
writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
|
|
writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
|
|
|
|
iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
|
|
}
|
|
|
|
/*
|
|
* This function writes the command buffer address to the hardware and
|
|
* enables it.
|
|
*/
|
|
static void iommu_enable_command_buffer(struct amd_iommu *iommu)
|
|
{
|
|
u64 entry;
|
|
|
|
BUG_ON(iommu->cmd_buf == NULL);
|
|
|
|
entry = (u64)virt_to_phys(iommu->cmd_buf);
|
|
entry |= MMIO_CMD_SIZE_512;
|
|
|
|
memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
|
|
&entry, sizeof(entry));
|
|
|
|
amd_iommu_reset_cmd_buffer(iommu);
|
|
iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
|
|
}
|
|
|
|
static void __init free_command_buffer(struct amd_iommu *iommu)
|
|
{
|
|
free_pages((unsigned long)iommu->cmd_buf,
|
|
get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
|
|
}
|
|
|
|
/* allocates the memory where the IOMMU will log its events to */
|
|
static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
|
|
{
|
|
iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
|
|
get_order(EVT_BUFFER_SIZE));
|
|
|
|
if (iommu->evt_buf == NULL)
|
|
return NULL;
|
|
|
|
iommu->evt_buf_size = EVT_BUFFER_SIZE;
|
|
|
|
return iommu->evt_buf;
|
|
}
|
|
|
|
static void iommu_enable_event_buffer(struct amd_iommu *iommu)
|
|
{
|
|
u64 entry;
|
|
|
|
BUG_ON(iommu->evt_buf == NULL);
|
|
|
|
entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
|
|
|
|
memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
|
|
&entry, sizeof(entry));
|
|
|
|
/* set head and tail to zero manually */
|
|
writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
|
|
writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
|
|
|
|
iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
|
|
}
|
|
|
|
static void __init free_event_buffer(struct amd_iommu *iommu)
|
|
{
|
|
free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
|
|
}
|
|
|
|
/* allocates the memory where the IOMMU will log its events to */
|
|
static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
|
|
{
|
|
iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
|
|
get_order(PPR_LOG_SIZE));
|
|
|
|
if (iommu->ppr_log == NULL)
|
|
return NULL;
|
|
|
|
return iommu->ppr_log;
|
|
}
|
|
|
|
static void iommu_enable_ppr_log(struct amd_iommu *iommu)
|
|
{
|
|
u64 entry;
|
|
|
|
if (iommu->ppr_log == NULL)
|
|
return;
|
|
|
|
entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
|
|
|
|
memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
|
|
&entry, sizeof(entry));
|
|
|
|
/* set head and tail to zero manually */
|
|
writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
|
|
writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
|
|
|
|
iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
|
|
iommu_feature_enable(iommu, CONTROL_PPR_EN);
|
|
}
|
|
|
|
static void __init free_ppr_log(struct amd_iommu *iommu)
|
|
{
|
|
if (iommu->ppr_log == NULL)
|
|
return;
|
|
|
|
free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
|
|
}
|
|
|
|
static void iommu_enable_gt(struct amd_iommu *iommu)
|
|
{
|
|
if (!iommu_feature(iommu, FEATURE_GT))
|
|
return;
|
|
|
|
iommu_feature_enable(iommu, CONTROL_GT_EN);
|
|
}
|
|
|
|
/* sets a specific bit in the device table entry. */
|
|
static void set_dev_entry_bit(u16 devid, u8 bit)
|
|
{
|
|
int i = (bit >> 6) & 0x03;
|
|
int _bit = bit & 0x3f;
|
|
|
|
amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
|
|
}
|
|
|
|
static int get_dev_entry_bit(u16 devid, u8 bit)
|
|
{
|
|
int i = (bit >> 6) & 0x03;
|
|
int _bit = bit & 0x3f;
|
|
|
|
return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
|
|
}
|
|
|
|
|
|
void amd_iommu_apply_erratum_63(u16 devid)
|
|
{
|
|
int sysmgt;
|
|
|
|
sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
|
|
(get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
|
|
|
|
if (sysmgt == 0x01)
|
|
set_dev_entry_bit(devid, DEV_ENTRY_IW);
|
|
}
|
|
|
|
/* Writes the specific IOMMU for a device into the rlookup table */
|
|
static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
|
|
{
|
|
amd_iommu_rlookup_table[devid] = iommu;
|
|
}
|
|
|
|
/*
|
|
* This function takes the device specific flags read from the ACPI
|
|
* table and sets up the device table entry with that information
|
|
*/
|
|
static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
|
|
u16 devid, u32 flags, u32 ext_flags)
|
|
{
|
|
if (flags & ACPI_DEVFLAG_INITPASS)
|
|
set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
|
|
if (flags & ACPI_DEVFLAG_EXTINT)
|
|
set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
|
|
if (flags & ACPI_DEVFLAG_NMI)
|
|
set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
|
|
if (flags & ACPI_DEVFLAG_SYSMGT1)
|
|
set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
|
|
if (flags & ACPI_DEVFLAG_SYSMGT2)
|
|
set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
|
|
if (flags & ACPI_DEVFLAG_LINT0)
|
|
set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
|
|
if (flags & ACPI_DEVFLAG_LINT1)
|
|
set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
|
|
|
|
amd_iommu_apply_erratum_63(devid);
|
|
|
|
set_iommu_for_device(iommu, devid);
|
|
}
|
|
|
|
static int add_special_device(u8 type, u8 id, u16 devid)
|
|
{
|
|
struct devid_map *entry;
|
|
struct list_head *list;
|
|
|
|
if (type != IVHD_SPECIAL_IOAPIC && type != IVHD_SPECIAL_HPET)
|
|
return -EINVAL;
|
|
|
|
entry = kzalloc(sizeof(*entry), GFP_KERNEL);
|
|
if (!entry)
|
|
return -ENOMEM;
|
|
|
|
entry->id = id;
|
|
entry->devid = devid;
|
|
|
|
if (type == IVHD_SPECIAL_IOAPIC)
|
|
list = &ioapic_map;
|
|
else
|
|
list = &hpet_map;
|
|
|
|
list_add_tail(&entry->list, list);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Reads the device exclusion range from ACPI and initializes the IOMMU with
|
|
* it
|
|
*/
|
|
static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
|
|
{
|
|
struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
|
|
|
|
if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
|
|
return;
|
|
|
|
if (iommu) {
|
|
/*
|
|
* We only can configure exclusion ranges per IOMMU, not
|
|
* per device. But we can enable the exclusion range per
|
|
* device. This is done here
|
|
*/
|
|
set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
|
|
iommu->exclusion_start = m->range_start;
|
|
iommu->exclusion_length = m->range_length;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Takes a pointer to an AMD IOMMU entry in the ACPI table and
|
|
* initializes the hardware and our data structures with it.
|
|
*/
|
|
static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
|
|
struct ivhd_header *h)
|
|
{
|
|
u8 *p = (u8 *)h;
|
|
u8 *end = p, flags = 0;
|
|
u16 devid = 0, devid_start = 0, devid_to = 0;
|
|
u32 dev_i, ext_flags = 0;
|
|
bool alias = false;
|
|
struct ivhd_entry *e;
|
|
|
|
/*
|
|
* First save the recommended feature enable bits from ACPI
|
|
*/
|
|
iommu->acpi_flags = h->flags;
|
|
|
|
/*
|
|
* Done. Now parse the device entries
|
|
*/
|
|
p += sizeof(struct ivhd_header);
|
|
end += h->length;
|
|
|
|
|
|
while (p < end) {
|
|
e = (struct ivhd_entry *)p;
|
|
switch (e->type) {
|
|
case IVHD_DEV_ALL:
|
|
|
|
DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
|
|
" last device %02x:%02x.%x flags: %02x\n",
|
|
PCI_BUS(iommu->first_device),
|
|
PCI_SLOT(iommu->first_device),
|
|
PCI_FUNC(iommu->first_device),
|
|
PCI_BUS(iommu->last_device),
|
|
PCI_SLOT(iommu->last_device),
|
|
PCI_FUNC(iommu->last_device),
|
|
e->flags);
|
|
|
|
for (dev_i = iommu->first_device;
|
|
dev_i <= iommu->last_device; ++dev_i)
|
|
set_dev_entry_from_acpi(iommu, dev_i,
|
|
e->flags, 0);
|
|
break;
|
|
case IVHD_DEV_SELECT:
|
|
|
|
DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
|
|
"flags: %02x\n",
|
|
PCI_BUS(e->devid),
|
|
PCI_SLOT(e->devid),
|
|
PCI_FUNC(e->devid),
|
|
e->flags);
|
|
|
|
devid = e->devid;
|
|
set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
|
|
break;
|
|
case IVHD_DEV_SELECT_RANGE_START:
|
|
|
|
DUMP_printk(" DEV_SELECT_RANGE_START\t "
|
|
"devid: %02x:%02x.%x flags: %02x\n",
|
|
PCI_BUS(e->devid),
|
|
PCI_SLOT(e->devid),
|
|
PCI_FUNC(e->devid),
|
|
e->flags);
|
|
|
|
devid_start = e->devid;
|
|
flags = e->flags;
|
|
ext_flags = 0;
|
|
alias = false;
|
|
break;
|
|
case IVHD_DEV_ALIAS:
|
|
|
|
DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
|
|
"flags: %02x devid_to: %02x:%02x.%x\n",
|
|
PCI_BUS(e->devid),
|
|
PCI_SLOT(e->devid),
|
|
PCI_FUNC(e->devid),
|
|
e->flags,
|
|
PCI_BUS(e->ext >> 8),
|
|
PCI_SLOT(e->ext >> 8),
|
|
PCI_FUNC(e->ext >> 8));
|
|
|
|
devid = e->devid;
|
|
devid_to = e->ext >> 8;
|
|
set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
|
|
set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
|
|
amd_iommu_alias_table[devid] = devid_to;
|
|
break;
|
|
case IVHD_DEV_ALIAS_RANGE:
|
|
|
|
DUMP_printk(" DEV_ALIAS_RANGE\t\t "
|
|
"devid: %02x:%02x.%x flags: %02x "
|
|
"devid_to: %02x:%02x.%x\n",
|
|
PCI_BUS(e->devid),
|
|
PCI_SLOT(e->devid),
|
|
PCI_FUNC(e->devid),
|
|
e->flags,
|
|
PCI_BUS(e->ext >> 8),
|
|
PCI_SLOT(e->ext >> 8),
|
|
PCI_FUNC(e->ext >> 8));
|
|
|
|
devid_start = e->devid;
|
|
flags = e->flags;
|
|
devid_to = e->ext >> 8;
|
|
ext_flags = 0;
|
|
alias = true;
|
|
break;
|
|
case IVHD_DEV_EXT_SELECT:
|
|
|
|
DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
|
|
"flags: %02x ext: %08x\n",
|
|
PCI_BUS(e->devid),
|
|
PCI_SLOT(e->devid),
|
|
PCI_FUNC(e->devid),
|
|
e->flags, e->ext);
|
|
|
|
devid = e->devid;
|
|
set_dev_entry_from_acpi(iommu, devid, e->flags,
|
|
e->ext);
|
|
break;
|
|
case IVHD_DEV_EXT_SELECT_RANGE:
|
|
|
|
DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
|
|
"%02x:%02x.%x flags: %02x ext: %08x\n",
|
|
PCI_BUS(e->devid),
|
|
PCI_SLOT(e->devid),
|
|
PCI_FUNC(e->devid),
|
|
e->flags, e->ext);
|
|
|
|
devid_start = e->devid;
|
|
flags = e->flags;
|
|
ext_flags = e->ext;
|
|
alias = false;
|
|
break;
|
|
case IVHD_DEV_RANGE_END:
|
|
|
|
DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
|
|
PCI_BUS(e->devid),
|
|
PCI_SLOT(e->devid),
|
|
PCI_FUNC(e->devid));
|
|
|
|
devid = e->devid;
|
|
for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
|
|
if (alias) {
|
|
amd_iommu_alias_table[dev_i] = devid_to;
|
|
set_dev_entry_from_acpi(iommu,
|
|
devid_to, flags, ext_flags);
|
|
}
|
|
set_dev_entry_from_acpi(iommu, dev_i,
|
|
flags, ext_flags);
|
|
}
|
|
break;
|
|
case IVHD_DEV_SPECIAL: {
|
|
u8 handle, type;
|
|
const char *var;
|
|
u16 devid;
|
|
int ret;
|
|
|
|
handle = e->ext & 0xff;
|
|
devid = (e->ext >> 8) & 0xffff;
|
|
type = (e->ext >> 24) & 0xff;
|
|
|
|
if (type == IVHD_SPECIAL_IOAPIC)
|
|
var = "IOAPIC";
|
|
else if (type == IVHD_SPECIAL_HPET)
|
|
var = "HPET";
|
|
else
|
|
var = "UNKNOWN";
|
|
|
|
DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
|
|
var, (int)handle,
|
|
PCI_BUS(devid),
|
|
PCI_SLOT(devid),
|
|
PCI_FUNC(devid));
|
|
|
|
set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
|
|
ret = add_special_device(type, handle, devid);
|
|
if (ret)
|
|
return ret;
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
|
|
p += ivhd_entry_length(p);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Initializes the device->iommu mapping for the driver */
|
|
static int __init init_iommu_devices(struct amd_iommu *iommu)
|
|
{
|
|
u32 i;
|
|
|
|
for (i = iommu->first_device; i <= iommu->last_device; ++i)
|
|
set_iommu_for_device(iommu, i);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __init free_iommu_one(struct amd_iommu *iommu)
|
|
{
|
|
free_command_buffer(iommu);
|
|
free_event_buffer(iommu);
|
|
free_ppr_log(iommu);
|
|
iommu_unmap_mmio_space(iommu);
|
|
}
|
|
|
|
static void __init free_iommu_all(void)
|
|
{
|
|
struct amd_iommu *iommu, *next;
|
|
|
|
for_each_iommu_safe(iommu, next) {
|
|
list_del(&iommu->list);
|
|
free_iommu_one(iommu);
|
|
kfree(iommu);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
|
|
* Workaround:
|
|
* BIOS should disable L2B micellaneous clock gating by setting
|
|
* L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
|
|
*/
|
|
static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
|
|
{
|
|
u32 value;
|
|
|
|
if ((boot_cpu_data.x86 != 0x15) ||
|
|
(boot_cpu_data.x86_model < 0x10) ||
|
|
(boot_cpu_data.x86_model > 0x1f))
|
|
return;
|
|
|
|
pci_write_config_dword(iommu->dev, 0xf0, 0x90);
|
|
pci_read_config_dword(iommu->dev, 0xf4, &value);
|
|
|
|
if (value & BIT(2))
|
|
return;
|
|
|
|
/* Select NB indirect register 0x90 and enable writing */
|
|
pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
|
|
|
|
pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
|
|
pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
|
|
dev_name(&iommu->dev->dev));
|
|
|
|
/* Clear the enable writing bit */
|
|
pci_write_config_dword(iommu->dev, 0xf0, 0x90);
|
|
}
|
|
|
|
/*
|
|
* This function clues the initialization function for one IOMMU
|
|
* together and also allocates the command buffer and programs the
|
|
* hardware. It does NOT enable the IOMMU. This is done afterwards.
|
|
*/
|
|
static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
|
|
{
|
|
int ret;
|
|
|
|
spin_lock_init(&iommu->lock);
|
|
|
|
/* Add IOMMU to internal data structures */
|
|
list_add_tail(&iommu->list, &amd_iommu_list);
|
|
iommu->index = amd_iommus_present++;
|
|
|
|
if (unlikely(iommu->index >= MAX_IOMMUS)) {
|
|
WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/* Index is fine - add IOMMU to the array */
|
|
amd_iommus[iommu->index] = iommu;
|
|
|
|
/*
|
|
* Copy data from ACPI table entry to the iommu struct
|
|
*/
|
|
iommu->devid = h->devid;
|
|
iommu->cap_ptr = h->cap_ptr;
|
|
iommu->pci_seg = h->pci_seg;
|
|
iommu->mmio_phys = h->mmio_phys;
|
|
iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
|
|
if (!iommu->mmio_base)
|
|
return -ENOMEM;
|
|
|
|
iommu->cmd_buf = alloc_command_buffer(iommu);
|
|
if (!iommu->cmd_buf)
|
|
return -ENOMEM;
|
|
|
|
iommu->evt_buf = alloc_event_buffer(iommu);
|
|
if (!iommu->evt_buf)
|
|
return -ENOMEM;
|
|
|
|
iommu->int_enabled = false;
|
|
|
|
ret = init_iommu_from_acpi(iommu, h);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Make sure IOMMU is not considered to translate itself. The IVRS
|
|
* table tells us so, but this is a lie!
|
|
*/
|
|
amd_iommu_rlookup_table[iommu->devid] = NULL;
|
|
|
|
init_iommu_devices(iommu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Iterates over all IOMMU entries in the ACPI table, allocates the
|
|
* IOMMU structure and initializes it with init_iommu_one()
|
|
*/
|
|
static int __init init_iommu_all(struct acpi_table_header *table)
|
|
{
|
|
u8 *p = (u8 *)table, *end = (u8 *)table;
|
|
struct ivhd_header *h;
|
|
struct amd_iommu *iommu;
|
|
int ret;
|
|
|
|
end += table->length;
|
|
p += IVRS_HEADER_LENGTH;
|
|
|
|
while (p < end) {
|
|
h = (struct ivhd_header *)p;
|
|
switch (*p) {
|
|
case ACPI_IVHD_TYPE:
|
|
|
|
DUMP_printk("device: %02x:%02x.%01x cap: %04x "
|
|
"seg: %d flags: %01x info %04x\n",
|
|
PCI_BUS(h->devid), PCI_SLOT(h->devid),
|
|
PCI_FUNC(h->devid), h->cap_ptr,
|
|
h->pci_seg, h->flags, h->info);
|
|
DUMP_printk(" mmio-addr: %016llx\n",
|
|
h->mmio_phys);
|
|
|
|
iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
|
|
if (iommu == NULL)
|
|
return -ENOMEM;
|
|
|
|
ret = init_iommu_one(iommu, h);
|
|
if (ret)
|
|
return ret;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
p += h->length;
|
|
|
|
}
|
|
WARN_ON(p != end);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int iommu_init_pci(struct amd_iommu *iommu)
|
|
{
|
|
int cap_ptr = iommu->cap_ptr;
|
|
u32 range, misc, low, high;
|
|
|
|
iommu->dev = pci_get_bus_and_slot(PCI_BUS(iommu->devid),
|
|
iommu->devid & 0xff);
|
|
if (!iommu->dev)
|
|
return -ENODEV;
|
|
|
|
pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
|
|
&iommu->cap);
|
|
pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
|
|
&range);
|
|
pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
|
|
&misc);
|
|
|
|
iommu->first_device = calc_devid(MMIO_GET_BUS(range),
|
|
MMIO_GET_FD(range));
|
|
iommu->last_device = calc_devid(MMIO_GET_BUS(range),
|
|
MMIO_GET_LD(range));
|
|
|
|
if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
|
|
amd_iommu_iotlb_sup = false;
|
|
|
|
/* read extended feature bits */
|
|
low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
|
|
high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
|
|
|
|
iommu->features = ((u64)high << 32) | low;
|
|
|
|
if (iommu_feature(iommu, FEATURE_GT)) {
|
|
int glxval;
|
|
u32 pasids;
|
|
u64 shift;
|
|
|
|
shift = iommu->features & FEATURE_PASID_MASK;
|
|
shift >>= FEATURE_PASID_SHIFT;
|
|
pasids = (1 << shift);
|
|
|
|
amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids);
|
|
|
|
glxval = iommu->features & FEATURE_GLXVAL_MASK;
|
|
glxval >>= FEATURE_GLXVAL_SHIFT;
|
|
|
|
if (amd_iommu_max_glx_val == -1)
|
|
amd_iommu_max_glx_val = glxval;
|
|
else
|
|
amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
|
|
}
|
|
|
|
if (iommu_feature(iommu, FEATURE_GT) &&
|
|
iommu_feature(iommu, FEATURE_PPR)) {
|
|
iommu->is_iommu_v2 = true;
|
|
amd_iommu_v2_present = true;
|
|
}
|
|
|
|
if (iommu_feature(iommu, FEATURE_PPR)) {
|
|
iommu->ppr_log = alloc_ppr_log(iommu);
|
|
if (!iommu->ppr_log)
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
|
|
amd_iommu_np_cache = true;
|
|
|
|
if (is_rd890_iommu(iommu->dev)) {
|
|
int i, j;
|
|
|
|
iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
|
|
PCI_DEVFN(0, 0));
|
|
|
|
/*
|
|
* Some rd890 systems may not be fully reconfigured by the
|
|
* BIOS, so it's necessary for us to store this information so
|
|
* it can be reprogrammed on resume
|
|
*/
|
|
pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
|
|
&iommu->stored_addr_lo);
|
|
pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
|
|
&iommu->stored_addr_hi);
|
|
|
|
/* Low bit locks writes to configuration space */
|
|
iommu->stored_addr_lo &= ~1;
|
|
|
|
for (i = 0; i < 6; i++)
|
|
for (j = 0; j < 0x12; j++)
|
|
iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
|
|
|
|
for (i = 0; i < 0x83; i++)
|
|
iommu->stored_l2[i] = iommu_read_l2(iommu, i);
|
|
}
|
|
|
|
amd_iommu_erratum_746_workaround(iommu);
|
|
|
|
return pci_enable_device(iommu->dev);
|
|
}
|
|
|
|
static void print_iommu_info(void)
|
|
{
|
|
static const char * const feat_str[] = {
|
|
"PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
|
|
"IA", "GA", "HE", "PC"
|
|
};
|
|
struct amd_iommu *iommu;
|
|
|
|
for_each_iommu(iommu) {
|
|
int i;
|
|
|
|
pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
|
|
dev_name(&iommu->dev->dev), iommu->cap_ptr);
|
|
|
|
if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
|
|
pr_info("AMD-Vi: Extended features: ");
|
|
for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
|
|
if (iommu_feature(iommu, (1ULL << i)))
|
|
pr_cont(" %s", feat_str[i]);
|
|
}
|
|
pr_cont("\n");
|
|
}
|
|
}
|
|
if (irq_remapping_enabled)
|
|
pr_info("AMD-Vi: Interrupt remapping enabled\n");
|
|
}
|
|
|
|
static int __init amd_iommu_init_pci(void)
|
|
{
|
|
struct amd_iommu *iommu;
|
|
int ret = 0;
|
|
|
|
for_each_iommu(iommu) {
|
|
ret = iommu_init_pci(iommu);
|
|
if (ret)
|
|
break;
|
|
}
|
|
|
|
ret = amd_iommu_init_devices();
|
|
|
|
print_iommu_info();
|
|
|
|
return ret;
|
|
}
|
|
|
|
/****************************************************************************
|
|
*
|
|
* The following functions initialize the MSI interrupts for all IOMMUs
|
|
* in the system. It's a bit challenging because there could be multiple
|
|
* IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
|
|
* pci_dev.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int iommu_setup_msi(struct amd_iommu *iommu)
|
|
{
|
|
int r;
|
|
|
|
r = pci_enable_msi(iommu->dev);
|
|
if (r)
|
|
return r;
|
|
|
|
r = request_threaded_irq(iommu->dev->irq,
|
|
amd_iommu_int_handler,
|
|
amd_iommu_int_thread,
|
|
0, "AMD-Vi",
|
|
iommu->dev);
|
|
|
|
if (r) {
|
|
pci_disable_msi(iommu->dev);
|
|
return r;
|
|
}
|
|
|
|
iommu->int_enabled = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int iommu_init_msi(struct amd_iommu *iommu)
|
|
{
|
|
int ret;
|
|
|
|
if (iommu->int_enabled)
|
|
goto enable_faults;
|
|
|
|
if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
|
|
ret = iommu_setup_msi(iommu);
|
|
else
|
|
ret = -ENODEV;
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
enable_faults:
|
|
iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
|
|
|
|
if (iommu->ppr_log != NULL)
|
|
iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/****************************************************************************
|
|
*
|
|
* The next functions belong to the third pass of parsing the ACPI
|
|
* table. In this last pass the memory mapping requirements are
|
|
* gathered (like exclusion and unity mapping ranges).
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void __init free_unity_maps(void)
|
|
{
|
|
struct unity_map_entry *entry, *next;
|
|
|
|
list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
|
|
list_del(&entry->list);
|
|
kfree(entry);
|
|
}
|
|
}
|
|
|
|
/* called when we find an exclusion range definition in ACPI */
|
|
static int __init init_exclusion_range(struct ivmd_header *m)
|
|
{
|
|
int i;
|
|
|
|
switch (m->type) {
|
|
case ACPI_IVMD_TYPE:
|
|
set_device_exclusion_range(m->devid, m);
|
|
break;
|
|
case ACPI_IVMD_TYPE_ALL:
|
|
for (i = 0; i <= amd_iommu_last_bdf; ++i)
|
|
set_device_exclusion_range(i, m);
|
|
break;
|
|
case ACPI_IVMD_TYPE_RANGE:
|
|
for (i = m->devid; i <= m->aux; ++i)
|
|
set_device_exclusion_range(i, m);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* called for unity map ACPI definition */
|
|
static int __init init_unity_map_range(struct ivmd_header *m)
|
|
{
|
|
struct unity_map_entry *e = NULL;
|
|
char *s;
|
|
|
|
e = kzalloc(sizeof(*e), GFP_KERNEL);
|
|
if (e == NULL)
|
|
return -ENOMEM;
|
|
|
|
switch (m->type) {
|
|
default:
|
|
kfree(e);
|
|
return 0;
|
|
case ACPI_IVMD_TYPE:
|
|
s = "IVMD_TYPEi\t\t\t";
|
|
e->devid_start = e->devid_end = m->devid;
|
|
break;
|
|
case ACPI_IVMD_TYPE_ALL:
|
|
s = "IVMD_TYPE_ALL\t\t";
|
|
e->devid_start = 0;
|
|
e->devid_end = amd_iommu_last_bdf;
|
|
break;
|
|
case ACPI_IVMD_TYPE_RANGE:
|
|
s = "IVMD_TYPE_RANGE\t\t";
|
|
e->devid_start = m->devid;
|
|
e->devid_end = m->aux;
|
|
break;
|
|
}
|
|
e->address_start = PAGE_ALIGN(m->range_start);
|
|
e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
|
|
e->prot = m->flags >> 1;
|
|
|
|
DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
|
|
" range_start: %016llx range_end: %016llx flags: %x\n", s,
|
|
PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
|
|
PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
|
|
PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
|
|
e->address_start, e->address_end, m->flags);
|
|
|
|
list_add_tail(&e->list, &amd_iommu_unity_map);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* iterates over all memory definitions we find in the ACPI table */
|
|
static int __init init_memory_definitions(struct acpi_table_header *table)
|
|
{
|
|
u8 *p = (u8 *)table, *end = (u8 *)table;
|
|
struct ivmd_header *m;
|
|
|
|
end += table->length;
|
|
p += IVRS_HEADER_LENGTH;
|
|
|
|
while (p < end) {
|
|
m = (struct ivmd_header *)p;
|
|
if (m->flags & IVMD_FLAG_EXCL_RANGE)
|
|
init_exclusion_range(m);
|
|
else if (m->flags & IVMD_FLAG_UNITY_MAP)
|
|
init_unity_map_range(m);
|
|
|
|
p += m->length;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Init the device table to not allow DMA access for devices and
|
|
* suppress all page faults
|
|
*/
|
|
static void init_device_table_dma(void)
|
|
{
|
|
u32 devid;
|
|
|
|
for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
|
|
set_dev_entry_bit(devid, DEV_ENTRY_VALID);
|
|
set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
|
|
}
|
|
}
|
|
|
|
static void __init uninit_device_table_dma(void)
|
|
{
|
|
u32 devid;
|
|
|
|
for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
|
|
amd_iommu_dev_table[devid].data[0] = 0ULL;
|
|
amd_iommu_dev_table[devid].data[1] = 0ULL;
|
|
}
|
|
}
|
|
|
|
static void init_device_table(void)
|
|
{
|
|
u32 devid;
|
|
|
|
if (!amd_iommu_irq_remap)
|
|
return;
|
|
|
|
for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
|
|
set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
|
|
}
|
|
|
|
static void iommu_init_flags(struct amd_iommu *iommu)
|
|
{
|
|
iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
|
|
iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
|
|
iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
|
|
|
|
iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
|
|
iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
|
|
iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
|
|
|
|
iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
|
|
iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
|
|
iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
|
|
|
|
iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
|
|
iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
|
|
iommu_feature_disable(iommu, CONTROL_ISOC_EN);
|
|
|
|
/*
|
|
* make IOMMU memory accesses cache coherent
|
|
*/
|
|
iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
|
|
|
|
/* Set IOTLB invalidation timeout to 1s */
|
|
iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
|
|
}
|
|
|
|
static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
|
|
{
|
|
int i, j;
|
|
u32 ioc_feature_control;
|
|
struct pci_dev *pdev = iommu->root_pdev;
|
|
|
|
/* RD890 BIOSes may not have completely reconfigured the iommu */
|
|
if (!is_rd890_iommu(iommu->dev) || !pdev)
|
|
return;
|
|
|
|
/*
|
|
* First, we need to ensure that the iommu is enabled. This is
|
|
* controlled by a register in the northbridge
|
|
*/
|
|
|
|
/* Select Northbridge indirect register 0x75 and enable writing */
|
|
pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
|
|
pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
|
|
|
|
/* Enable the iommu */
|
|
if (!(ioc_feature_control & 0x1))
|
|
pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
|
|
|
|
/* Restore the iommu BAR */
|
|
pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
|
|
iommu->stored_addr_lo);
|
|
pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
|
|
iommu->stored_addr_hi);
|
|
|
|
/* Restore the l1 indirect regs for each of the 6 l1s */
|
|
for (i = 0; i < 6; i++)
|
|
for (j = 0; j < 0x12; j++)
|
|
iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
|
|
|
|
/* Restore the l2 indirect regs */
|
|
for (i = 0; i < 0x83; i++)
|
|
iommu_write_l2(iommu, i, iommu->stored_l2[i]);
|
|
|
|
/* Lock PCI setup registers */
|
|
pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
|
|
iommu->stored_addr_lo | 1);
|
|
}
|
|
|
|
/*
|
|
* This function finally enables all IOMMUs found in the system after
|
|
* they have been initialized
|
|
*/
|
|
static void early_enable_iommus(void)
|
|
{
|
|
struct amd_iommu *iommu;
|
|
|
|
for_each_iommu(iommu) {
|
|
iommu_disable(iommu);
|
|
iommu_init_flags(iommu);
|
|
iommu_set_device_table(iommu);
|
|
iommu_enable_command_buffer(iommu);
|
|
iommu_enable_event_buffer(iommu);
|
|
iommu_set_exclusion_range(iommu);
|
|
iommu_enable(iommu);
|
|
iommu_flush_all_caches(iommu);
|
|
}
|
|
}
|
|
|
|
static void enable_iommus_v2(void)
|
|
{
|
|
struct amd_iommu *iommu;
|
|
|
|
for_each_iommu(iommu) {
|
|
iommu_enable_ppr_log(iommu);
|
|
iommu_enable_gt(iommu);
|
|
}
|
|
}
|
|
|
|
static void enable_iommus(void)
|
|
{
|
|
early_enable_iommus();
|
|
|
|
enable_iommus_v2();
|
|
}
|
|
|
|
static void disable_iommus(void)
|
|
{
|
|
struct amd_iommu *iommu;
|
|
|
|
for_each_iommu(iommu)
|
|
iommu_disable(iommu);
|
|
}
|
|
|
|
/*
|
|
* Suspend/Resume support
|
|
* disable suspend until real resume implemented
|
|
*/
|
|
|
|
static void amd_iommu_resume(void)
|
|
{
|
|
struct amd_iommu *iommu;
|
|
|
|
for_each_iommu(iommu)
|
|
iommu_apply_resume_quirks(iommu);
|
|
|
|
/* re-load the hardware */
|
|
enable_iommus();
|
|
|
|
amd_iommu_enable_interrupts();
|
|
}
|
|
|
|
static int amd_iommu_suspend(void)
|
|
{
|
|
/* disable IOMMUs to go out of the way for BIOS */
|
|
disable_iommus();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct syscore_ops amd_iommu_syscore_ops = {
|
|
.suspend = amd_iommu_suspend,
|
|
.resume = amd_iommu_resume,
|
|
};
|
|
|
|
static void __init free_on_init_error(void)
|
|
{
|
|
free_pages((unsigned long)irq_lookup_table,
|
|
get_order(rlookup_table_size));
|
|
|
|
if (amd_iommu_irq_cache) {
|
|
kmem_cache_destroy(amd_iommu_irq_cache);
|
|
amd_iommu_irq_cache = NULL;
|
|
|
|
}
|
|
|
|
free_pages((unsigned long)amd_iommu_rlookup_table,
|
|
get_order(rlookup_table_size));
|
|
|
|
free_pages((unsigned long)amd_iommu_alias_table,
|
|
get_order(alias_table_size));
|
|
|
|
free_pages((unsigned long)amd_iommu_dev_table,
|
|
get_order(dev_table_size));
|
|
|
|
free_iommu_all();
|
|
|
|
#ifdef CONFIG_GART_IOMMU
|
|
/*
|
|
* We failed to initialize the AMD IOMMU - try fallback to GART
|
|
* if possible.
|
|
*/
|
|
gart_iommu_init();
|
|
|
|
#endif
|
|
}
|
|
|
|
/* SB IOAPIC is always on this device in AMD systems */
|
|
#define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
|
|
|
|
static bool __init check_ioapic_information(void)
|
|
{
|
|
bool ret, has_sb_ioapic;
|
|
int idx;
|
|
|
|
has_sb_ioapic = false;
|
|
ret = false;
|
|
|
|
for (idx = 0; idx < nr_ioapics; idx++) {
|
|
int devid, id = mpc_ioapic_id(idx);
|
|
|
|
devid = get_ioapic_devid(id);
|
|
if (devid < 0) {
|
|
pr_err(FW_BUG "AMD-Vi: IOAPIC[%d] not in IVRS table\n", id);
|
|
ret = false;
|
|
} else if (devid == IOAPIC_SB_DEVID) {
|
|
has_sb_ioapic = true;
|
|
ret = true;
|
|
}
|
|
}
|
|
|
|
if (!has_sb_ioapic) {
|
|
/*
|
|
* We expect the SB IOAPIC to be listed in the IVRS
|
|
* table. The system timer is connected to the SB IOAPIC
|
|
* and if we don't have it in the list the system will
|
|
* panic at boot time. This situation usually happens
|
|
* when the BIOS is buggy and provides us the wrong
|
|
* device id for the IOAPIC in the system.
|
|
*/
|
|
pr_err(FW_BUG "AMD-Vi: No southbridge IOAPIC found in IVRS table\n");
|
|
}
|
|
|
|
if (!ret)
|
|
pr_err("AMD-Vi: Disabling interrupt remapping due to BIOS Bug(s)\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __init free_dma_resources(void)
|
|
{
|
|
amd_iommu_uninit_devices();
|
|
|
|
free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
|
|
get_order(MAX_DOMAIN_ID/8));
|
|
|
|
free_unity_maps();
|
|
}
|
|
|
|
/*
|
|
* This is the hardware init function for AMD IOMMU in the system.
|
|
* This function is called either from amd_iommu_init or from the interrupt
|
|
* remapping setup code.
|
|
*
|
|
* This function basically parses the ACPI table for AMD IOMMU (IVRS)
|
|
* three times:
|
|
*
|
|
* 1 pass) Find the highest PCI device id the driver has to handle.
|
|
* Upon this information the size of the data structures is
|
|
* determined that needs to be allocated.
|
|
*
|
|
* 2 pass) Initialize the data structures just allocated with the
|
|
* information in the ACPI table about available AMD IOMMUs
|
|
* in the system. It also maps the PCI devices in the
|
|
* system to specific IOMMUs
|
|
*
|
|
* 3 pass) After the basic data structures are allocated and
|
|
* initialized we update them with information about memory
|
|
* remapping requirements parsed out of the ACPI table in
|
|
* this last pass.
|
|
*
|
|
* After everything is set up the IOMMUs are enabled and the necessary
|
|
* hotplug and suspend notifiers are registered.
|
|
*/
|
|
static int __init early_amd_iommu_init(void)
|
|
{
|
|
struct acpi_table_header *ivrs_base;
|
|
acpi_size ivrs_size;
|
|
acpi_status status;
|
|
int i, ret = 0;
|
|
|
|
if (!amd_iommu_detected)
|
|
return -ENODEV;
|
|
|
|
status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
|
|
if (status == AE_NOT_FOUND)
|
|
return -ENODEV;
|
|
else if (ACPI_FAILURE(status)) {
|
|
const char *err = acpi_format_exception(status);
|
|
pr_err("AMD-Vi: IVRS table error: %s\n", err);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* First parse ACPI tables to find the largest Bus/Dev/Func
|
|
* we need to handle. Upon this information the shared data
|
|
* structures for the IOMMUs in the system will be allocated
|
|
*/
|
|
ret = find_last_devid_acpi(ivrs_base);
|
|
if (ret)
|
|
goto out;
|
|
|
|
dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
|
|
alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
|
|
rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
|
|
|
|
/* Device table - directly used by all IOMMUs */
|
|
ret = -ENOMEM;
|
|
amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
|
|
get_order(dev_table_size));
|
|
if (amd_iommu_dev_table == NULL)
|
|
goto out;
|
|
|
|
/*
|
|
* Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
|
|
* IOMMU see for that device
|
|
*/
|
|
amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
|
|
get_order(alias_table_size));
|
|
if (amd_iommu_alias_table == NULL)
|
|
goto out;
|
|
|
|
/* IOMMU rlookup table - find the IOMMU for a specific device */
|
|
amd_iommu_rlookup_table = (void *)__get_free_pages(
|
|
GFP_KERNEL | __GFP_ZERO,
|
|
get_order(rlookup_table_size));
|
|
if (amd_iommu_rlookup_table == NULL)
|
|
goto out;
|
|
|
|
amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
|
|
GFP_KERNEL | __GFP_ZERO,
|
|
get_order(MAX_DOMAIN_ID/8));
|
|
if (amd_iommu_pd_alloc_bitmap == NULL)
|
|
goto out;
|
|
|
|
/*
|
|
* let all alias entries point to itself
|
|
*/
|
|
for (i = 0; i <= amd_iommu_last_bdf; ++i)
|
|
amd_iommu_alias_table[i] = i;
|
|
|
|
/*
|
|
* never allocate domain 0 because its used as the non-allocated and
|
|
* error value placeholder
|
|
*/
|
|
amd_iommu_pd_alloc_bitmap[0] = 1;
|
|
|
|
spin_lock_init(&amd_iommu_pd_lock);
|
|
|
|
/*
|
|
* now the data structures are allocated and basically initialized
|
|
* start the real acpi table scan
|
|
*/
|
|
ret = init_iommu_all(ivrs_base);
|
|
if (ret)
|
|
goto out;
|
|
|
|
if (amd_iommu_irq_remap)
|
|
amd_iommu_irq_remap = check_ioapic_information();
|
|
|
|
if (amd_iommu_irq_remap) {
|
|
/*
|
|
* Interrupt remapping enabled, create kmem_cache for the
|
|
* remapping tables.
|
|
*/
|
|
amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
|
|
MAX_IRQS_PER_TABLE * sizeof(u32),
|
|
IRQ_TABLE_ALIGNMENT,
|
|
0, NULL);
|
|
if (!amd_iommu_irq_cache)
|
|
goto out;
|
|
|
|
irq_lookup_table = (void *)__get_free_pages(
|
|
GFP_KERNEL | __GFP_ZERO,
|
|
get_order(rlookup_table_size));
|
|
if (!irq_lookup_table)
|
|
goto out;
|
|
}
|
|
|
|
ret = init_memory_definitions(ivrs_base);
|
|
if (ret)
|
|
goto out;
|
|
|
|
/* init the device table */
|
|
init_device_table();
|
|
|
|
out:
|
|
/* Don't leak any ACPI memory */
|
|
early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
|
|
ivrs_base = NULL;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int amd_iommu_enable_interrupts(void)
|
|
{
|
|
struct amd_iommu *iommu;
|
|
int ret = 0;
|
|
|
|
for_each_iommu(iommu) {
|
|
ret = iommu_init_msi(iommu);
|
|
if (ret)
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static bool detect_ivrs(void)
|
|
{
|
|
struct acpi_table_header *ivrs_base;
|
|
acpi_size ivrs_size;
|
|
acpi_status status;
|
|
|
|
status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
|
|
if (status == AE_NOT_FOUND)
|
|
return false;
|
|
else if (ACPI_FAILURE(status)) {
|
|
const char *err = acpi_format_exception(status);
|
|
pr_err("AMD-Vi: IVRS table error: %s\n", err);
|
|
return false;
|
|
}
|
|
|
|
early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
|
|
|
|
/* Make sure ACS will be enabled during PCI probe */
|
|
pci_request_acs();
|
|
|
|
if (!disable_irq_remap)
|
|
amd_iommu_irq_remap = true;
|
|
|
|
return true;
|
|
}
|
|
|
|
static int amd_iommu_init_dma(void)
|
|
{
|
|
struct amd_iommu *iommu;
|
|
int ret;
|
|
|
|
if (iommu_pass_through)
|
|
ret = amd_iommu_init_passthrough();
|
|
else
|
|
ret = amd_iommu_init_dma_ops();
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
init_device_table_dma();
|
|
|
|
for_each_iommu(iommu)
|
|
iommu_flush_all_caches(iommu);
|
|
|
|
amd_iommu_init_api();
|
|
|
|
amd_iommu_init_notifier();
|
|
|
|
return 0;
|
|
}
|
|
|
|
/****************************************************************************
|
|
*
|
|
* AMD IOMMU Initialization State Machine
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int __init state_next(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (init_state) {
|
|
case IOMMU_START_STATE:
|
|
if (!detect_ivrs()) {
|
|
init_state = IOMMU_NOT_FOUND;
|
|
ret = -ENODEV;
|
|
} else {
|
|
init_state = IOMMU_IVRS_DETECTED;
|
|
}
|
|
break;
|
|
case IOMMU_IVRS_DETECTED:
|
|
ret = early_amd_iommu_init();
|
|
init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
|
|
break;
|
|
case IOMMU_ACPI_FINISHED:
|
|
early_enable_iommus();
|
|
register_syscore_ops(&amd_iommu_syscore_ops);
|
|
x86_platform.iommu_shutdown = disable_iommus;
|
|
init_state = IOMMU_ENABLED;
|
|
break;
|
|
case IOMMU_ENABLED:
|
|
ret = amd_iommu_init_pci();
|
|
init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
|
|
enable_iommus_v2();
|
|
break;
|
|
case IOMMU_PCI_INIT:
|
|
ret = amd_iommu_enable_interrupts();
|
|
init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
|
|
break;
|
|
case IOMMU_INTERRUPTS_EN:
|
|
ret = amd_iommu_init_dma();
|
|
init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
|
|
break;
|
|
case IOMMU_DMA_OPS:
|
|
init_state = IOMMU_INITIALIZED;
|
|
break;
|
|
case IOMMU_INITIALIZED:
|
|
/* Nothing to do */
|
|
break;
|
|
case IOMMU_NOT_FOUND:
|
|
case IOMMU_INIT_ERROR:
|
|
/* Error states => do nothing */
|
|
ret = -EINVAL;
|
|
break;
|
|
default:
|
|
/* Unknown state */
|
|
BUG();
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __init iommu_go_to_state(enum iommu_init_state state)
|
|
{
|
|
int ret = 0;
|
|
|
|
while (init_state != state) {
|
|
ret = state_next();
|
|
if (init_state == IOMMU_NOT_FOUND ||
|
|
init_state == IOMMU_INIT_ERROR)
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_IRQ_REMAP
|
|
int __init amd_iommu_prepare(void)
|
|
{
|
|
return iommu_go_to_state(IOMMU_ACPI_FINISHED);
|
|
}
|
|
|
|
int __init amd_iommu_supported(void)
|
|
{
|
|
return amd_iommu_irq_remap ? 1 : 0;
|
|
}
|
|
|
|
int __init amd_iommu_enable(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = iommu_go_to_state(IOMMU_ENABLED);
|
|
if (ret)
|
|
return ret;
|
|
|
|
irq_remapping_enabled = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void amd_iommu_disable(void)
|
|
{
|
|
amd_iommu_suspend();
|
|
}
|
|
|
|
int amd_iommu_reenable(int mode)
|
|
{
|
|
amd_iommu_resume();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int __init amd_iommu_enable_faulting(void)
|
|
{
|
|
/* We enable MSI later when PCI is initialized */
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* This is the core init function for AMD IOMMU hardware in the system.
|
|
* This function is called from the generic x86 DMA layer initialization
|
|
* code.
|
|
*/
|
|
static int __init amd_iommu_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = iommu_go_to_state(IOMMU_INITIALIZED);
|
|
if (ret) {
|
|
free_dma_resources();
|
|
if (!irq_remapping_enabled) {
|
|
disable_iommus();
|
|
free_on_init_error();
|
|
} else {
|
|
struct amd_iommu *iommu;
|
|
|
|
uninit_device_table_dma();
|
|
for_each_iommu(iommu)
|
|
iommu_flush_all_caches(iommu);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/****************************************************************************
|
|
*
|
|
* Early detect code. This code runs at IOMMU detection time in the DMA
|
|
* layer. It just looks if there is an IVRS ACPI table to detect AMD
|
|
* IOMMUs
|
|
*
|
|
****************************************************************************/
|
|
int __init amd_iommu_detect(void)
|
|
{
|
|
int ret;
|
|
|
|
if (no_iommu || (iommu_detected && !gart_iommu_aperture))
|
|
return -ENODEV;
|
|
|
|
if (amd_iommu_disabled)
|
|
return -ENODEV;
|
|
|
|
ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
|
|
if (ret)
|
|
return ret;
|
|
|
|
amd_iommu_detected = true;
|
|
iommu_detected = 1;
|
|
x86_init.iommu.iommu_init = amd_iommu_init;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/****************************************************************************
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*
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* Parsing functions for the AMD IOMMU specific kernel command line
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* options.
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*
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****************************************************************************/
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static int __init parse_amd_iommu_dump(char *str)
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{
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amd_iommu_dump = true;
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return 1;
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}
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static int __init parse_amd_iommu_options(char *str)
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{
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for (; *str; ++str) {
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if (strncmp(str, "fullflush", 9) == 0)
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amd_iommu_unmap_flush = true;
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if (strncmp(str, "off", 3) == 0)
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amd_iommu_disabled = true;
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if (strncmp(str, "force_isolation", 15) == 0)
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amd_iommu_force_isolation = true;
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}
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return 1;
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}
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__setup("amd_iommu_dump", parse_amd_iommu_dump);
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__setup("amd_iommu=", parse_amd_iommu_options);
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IOMMU_INIT_FINISH(amd_iommu_detect,
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gart_iommu_hole_init,
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NULL,
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NULL);
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bool amd_iommu_v2_supported(void)
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{
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return amd_iommu_v2_present;
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}
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EXPORT_SYMBOL(amd_iommu_v2_supported);
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