linux-sg2042/drivers/cxl
Dan Williams a371788d4f cxl/pmem: Fix nvdimm registration races
commit f57aec443c upstream.

A loop of the form:

    while true; do modprobe cxl_pci; modprobe -r cxl_pci; done

...fails with the following crash signature:

    BUG: kernel NULL pointer dereference, address: 0000000000000040
    [..]
    RIP: 0010:cxl_internal_send_cmd+0x5/0xb0 [cxl_core]
    [..]
    Call Trace:
     <TASK>
     cxl_pmem_ctl+0x121/0x240 [cxl_pmem]
     nvdimm_get_config_data+0xd6/0x1a0 [libnvdimm]
     nd_label_data_init+0x135/0x7e0 [libnvdimm]
     nvdimm_probe+0xd6/0x1c0 [libnvdimm]
     nvdimm_bus_probe+0x7a/0x1e0 [libnvdimm]
     really_probe+0xde/0x380
     __driver_probe_device+0x78/0x170
     driver_probe_device+0x1f/0x90
     __device_attach_driver+0x85/0x110
     bus_for_each_drv+0x7d/0xc0
     __device_attach+0xb4/0x1e0
     bus_probe_device+0x9f/0xc0
     device_add+0x445/0x9c0
     nd_async_device_register+0xe/0x40 [libnvdimm]
     async_run_entry_fn+0x30/0x130

...namely that the bottom half of async nvdimm device registration runs
after the CXL has already torn down the context that cxl_pmem_ctl()
needs. Unlike the ACPI NFIT case that benefits from launching multiple
nvdimm device registrations in parallel from those listed in the table,
CXL is already marked PROBE_PREFER_ASYNCHRONOUS. So provide for a
synchronous registration path to preclude this scenario.

Fixes: 21083f5152 ("cxl/pmem: Register 'pmem' / cxl_nvdimm devices")
Cc: <stable@vger.kernel.org>
Reported-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-03-10 09:34:20 +01:00
..
core cxl/region: Fix passthrough-decoder detection 2023-02-14 19:11:52 +01:00
Kconfig cxl/region: Allocate HPA capacity to regions 2022-07-25 12:18:06 -07:00
Makefile PM: CXL: Disable suspend 2022-04-22 16:09:42 -07:00
acpi.c cxl/acpi: Minimize granularity for x1 interleaves 2022-08-01 15:36:33 -07:00
cxl.h cxl/region: Fix 'distance' calculation with passthrough ports 2022-11-04 16:01:24 -07:00
cxlmem.h cxl/region: Attach endpoint decoders 2022-07-25 12:18:07 -07:00
cxlpci.h cxl/port: Read CDAT table 2022-07-19 15:38:05 -07:00
mem.c cxl/mem: Enumerate port targets before adding endpoints 2022-07-21 17:19:25 -07:00
pci.c cxl/pci: Create PCI DOE mailbox's for memory devices 2022-07-19 15:38:04 -07:00
pmem.c cxl/pmem: Fix nvdimm registration races 2023-03-10 09:34:20 +01:00
port.c cxl/port: Read CDAT table 2022-07-19 15:38:05 -07:00