331 lines
8.2 KiB
C
331 lines
8.2 KiB
C
/*
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* Chip-specific setup code for the AT91SAM9x5 family
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*
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* Copyright (C) 2010-2012 Atmel Corporation.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/at91sam9x5.h>
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#include <mach/at91_pmc.h>
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#include <mach/cpu.h>
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#include <mach/board.h>
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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#include "sam9_smc.h"
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioAB_clk = {
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.name = "pioAB_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioCD_clk = {
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.name = "pioCD_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk smd_clk = {
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.name = "smd_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_SMD,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_USART0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_USART1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_USART2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* USART3 clock - Only for sam9g25/sam9x25 */
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_USART3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi0_clk = {
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.name = "twi0_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi1_clk = {
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.name = "twi1_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi2_clk = {
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.name = "twi2_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc0_clk = {
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.name = "mci0_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uart0_clk = {
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.name = "uart0_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_UART0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uart1_clk = {
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.name = "uart1_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_UART1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tcb0_clk = {
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.name = "tcb0_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_TCB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_PWM,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk adc_clk = {
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.name = "adc_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_ADC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk adc_op_clk = {
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.name = "adc_op_clk",
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.type = CLK_TYPE_PERIPHERAL,
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.rate_hz = 5000000,
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};
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static struct clk dma0_clk = {
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.name = "dma0_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk dma1_clk = {
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.name = "dma1_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uhphs_clk = {
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.name = "uhphs",
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.pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udphs_clk = {
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.name = "udphs_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
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static struct clk macb0_clk = {
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.name = "pclk",
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.pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* isi clock - Only for sam9g25 */
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static struct clk isi_clk = {
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.name = "isi_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_ISI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc1_clk = {
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.name = "mci1_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* emac1 clock - Only for sam9x25 */
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static struct clk macb1_clk = {
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.name = "pclk",
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.pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc_clk = {
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.name = "ssc_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_SSC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* can0 clock - Only for sam9x35 */
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static struct clk can0_clk = {
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.name = "can0_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* can1 clock - Only for sam9x35 */
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static struct clk can1_clk = {
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.name = "can1_clk",
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.pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioAB_clk,
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&pioCD_clk,
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&smd_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&twi0_clk,
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&twi1_clk,
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&twi2_clk,
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&mmc0_clk,
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&spi0_clk,
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&spi1_clk,
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&uart0_clk,
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&uart1_clk,
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&tcb0_clk,
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&pwm_clk,
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&adc_clk,
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&adc_op_clk,
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&dma0_clk,
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&dma1_clk,
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&uhphs_clk,
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&udphs_clk,
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&mmc1_clk,
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&ssc_clk,
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// irq0
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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/* lookup table for DT entries */
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CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
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CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
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CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
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CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
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CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
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CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
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CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
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CLKDEV_CON_ID("pioA", &pioAB_clk),
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CLKDEV_CON_ID("pioB", &pioAB_clk),
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CLKDEV_CON_ID("pioC", &pioCD_clk),
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CLKDEV_CON_ID("pioD", &pioCD_clk),
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/* additional fake clock for macb_hclk */
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CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
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CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
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CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
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CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
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CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
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};
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/*
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* The two programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static void __init at91sam9x5_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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if (cpu_is_at91sam9g25()
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|| cpu_is_at91sam9x25())
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clk_register(&usart3_clk);
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if (cpu_is_at91sam9g25()
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|| cpu_is_at91sam9x25()
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|| cpu_is_at91sam9g35()
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|| cpu_is_at91sam9x35())
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clk_register(&macb0_clk);
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if (cpu_is_at91sam9g15()
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|| cpu_is_at91sam9g35()
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|| cpu_is_at91sam9x35())
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clk_register(&lcdc_clk);
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if (cpu_is_at91sam9g25())
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clk_register(&isi_clk);
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if (cpu_is_at91sam9x25())
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clk_register(&macb1_clk);
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if (cpu_is_at91sam9x25()
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|| cpu_is_at91sam9x35()) {
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clk_register(&can0_clk);
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clk_register(&can1_clk);
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}
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clk_register(&pck0);
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clk_register(&pck1);
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}
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/* --------------------------------------------------------------------
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* AT91SAM9x5 processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91sam9x5_map_io(void)
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{
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at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
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}
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void __init at91sam9x5_initialize(void)
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{
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/* Register GPIO subsystem (using DT) */
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at91_gpio_init(NULL, 0);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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struct at91_init_soc __initdata at91sam9x5_soc = {
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.map_io = at91sam9x5_map_io,
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.register_clocks = at91sam9x5_register_clocks,
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.init = at91sam9x5_initialize,
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};
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