Lior Amsalem da497f6fba ARM: mvebu: Align the internal registers virtual base to support LPAE ... In order to be able to support the LPAE, the internal registers virtual base must be aligned to 2MB. In LPAE section size is 2MB, in earlyprintk we map the internal registers and it must be section aligned. Signed-off-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>		2013-04-15 14:06:59 +00:00
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asm	Fixes:	2013-03-12 20:25:53 -07:00
debug	ARM: mvebu: Align the internal registers virtual base to support LPAE	2013-04-15 14:06:59 +00:00
uapi/asm	ARM: 7665/1: Wire up kcmp syscall	2013-03-03 22:54:18 +00:00