318 lines
8.4 KiB
C
318 lines
8.4 KiB
C
/*
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* Renesas R-Car Gen3 for USB2.0 PHY driver
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*
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* Copyright (C) 2015 Renesas Electronics Corporation
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*
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* This is based on the phy-rcar-gen2 driver:
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* Copyright (C) 2014 Renesas Solutions Corp.
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* Copyright (C) 2014 Cogent Embedded, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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/******* USB2.0 Host registers (original offset is +0x200) *******/
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#define USB2_INT_ENABLE 0x000
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#define USB2_USBCTR 0x00c
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#define USB2_SPD_RSM_TIMSET 0x10c
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#define USB2_OC_TIMSET 0x110
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#define USB2_COMMCTRL 0x600
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#define USB2_OBINTSTA 0x604
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#define USB2_OBINTEN 0x608
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#define USB2_VBCTRL 0x60c
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#define USB2_LINECTRL1 0x610
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#define USB2_ADPCTRL 0x630
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/* INT_ENABLE */
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#define USB2_INT_ENABLE_UCOM_INTEN BIT(3)
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#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2)
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#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1)
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#define USB2_INT_ENABLE_INIT (USB2_INT_ENABLE_UCOM_INTEN | \
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USB2_INT_ENABLE_USBH_INTB_EN | \
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USB2_INT_ENABLE_USBH_INTA_EN)
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/* USBCTR */
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#define USB2_USBCTR_DIRPD BIT(2)
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#define USB2_USBCTR_PLL_RST BIT(1)
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/* SPD_RSM_TIMSET */
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#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
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/* OC_TIMSET */
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#define USB2_OC_TIMSET_INIT 0x000209ab
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/* COMMCTRL */
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#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
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/* OBINTSTA and OBINTEN */
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#define USB2_OBINT_SESSVLDCHG BIT(12)
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#define USB2_OBINT_IDDIGCHG BIT(11)
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#define USB2_OBINT_BITS (USB2_OBINT_SESSVLDCHG | \
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USB2_OBINT_IDDIGCHG)
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/* VBCTRL */
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#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
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/* LINECTRL1 */
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#define USB2_LINECTRL1_DPRPD_EN BIT(19)
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#define USB2_LINECTRL1_DP_RPD BIT(18)
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#define USB2_LINECTRL1_DMRPD_EN BIT(17)
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#define USB2_LINECTRL1_DM_RPD BIT(16)
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/* ADPCTRL */
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#define USB2_ADPCTRL_OTGSESSVLD BIT(20)
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#define USB2_ADPCTRL_IDDIG BIT(19)
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#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
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#define USB2_ADPCTRL_DRVVBUS BIT(4)
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struct rcar_gen3_data {
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void __iomem *base;
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struct clk *clk;
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};
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struct rcar_gen3_chan {
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struct rcar_gen3_data usb2;
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struct phy *phy;
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bool has_otg;
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};
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static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
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{
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void __iomem *usb2_base = ch->usb2.base;
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u32 val = readl(usb2_base + USB2_COMMCTRL);
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dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, host);
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if (host)
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val &= ~USB2_COMMCTRL_OTG_PERI;
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else
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val |= USB2_COMMCTRL_OTG_PERI;
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writel(val, usb2_base + USB2_COMMCTRL);
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}
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static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
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{
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void __iomem *usb2_base = ch->usb2.base;
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u32 val = readl(usb2_base + USB2_LINECTRL1);
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dev_vdbg(&ch->phy->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm);
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val &= ~(USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
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if (dp)
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val |= USB2_LINECTRL1_DP_RPD;
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if (dm)
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val |= USB2_LINECTRL1_DM_RPD;
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writel(val, usb2_base + USB2_LINECTRL1);
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}
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static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
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{
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void __iomem *usb2_base = ch->usb2.base;
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u32 val = readl(usb2_base + USB2_ADPCTRL);
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dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, vbus);
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if (vbus)
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val |= USB2_ADPCTRL_DRVVBUS;
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else
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val &= ~USB2_ADPCTRL_DRVVBUS;
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writel(val, usb2_base + USB2_ADPCTRL);
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}
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static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch)
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{
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rcar_gen3_set_linectrl(ch, 1, 1);
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rcar_gen3_set_host_mode(ch, 1);
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rcar_gen3_enable_vbus_ctrl(ch, 1);
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}
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static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch)
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{
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rcar_gen3_set_linectrl(ch, 0, 1);
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rcar_gen3_set_host_mode(ch, 0);
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rcar_gen3_enable_vbus_ctrl(ch, 0);
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}
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static bool rcar_gen3_check_vbus(struct rcar_gen3_chan *ch)
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{
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return !!(readl(ch->usb2.base + USB2_ADPCTRL) &
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USB2_ADPCTRL_OTGSESSVLD);
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}
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static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
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{
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return !!(readl(ch->usb2.base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
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}
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static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch)
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{
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bool is_host = true;
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/* B-device? */
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if (rcar_gen3_check_id(ch) && rcar_gen3_check_vbus(ch))
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is_host = false;
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if (is_host)
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rcar_gen3_init_for_host(ch);
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else
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rcar_gen3_init_for_peri(ch);
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}
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static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
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{
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void __iomem *usb2_base = ch->usb2.base;
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u32 val;
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val = readl(usb2_base + USB2_VBCTRL);
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writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
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writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
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val = readl(usb2_base + USB2_OBINTEN);
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writel(val | USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
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val = readl(usb2_base + USB2_ADPCTRL);
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writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
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val = readl(usb2_base + USB2_LINECTRL1);
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rcar_gen3_set_linectrl(ch, 0, 0);
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writel(val | USB2_LINECTRL1_DPRPD_EN | USB2_LINECTRL1_DMRPD_EN,
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usb2_base + USB2_LINECTRL1);
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rcar_gen3_device_recognition(ch);
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}
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static int rcar_gen3_phy_usb2_init(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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void __iomem *usb2_base = channel->usb2.base;
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/* Initialize USB2 part */
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writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
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writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
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writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
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/* Initialize otg part */
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if (channel->has_otg)
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rcar_gen3_init_otg(channel);
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return 0;
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}
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static int rcar_gen3_phy_usb2_exit(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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writel(0, channel->usb2.base + USB2_INT_ENABLE);
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return 0;
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}
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static int rcar_gen3_phy_usb2_power_on(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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void __iomem *usb2_base = channel->usb2.base;
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u32 val;
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val = readl(usb2_base + USB2_USBCTR);
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val |= USB2_USBCTR_PLL_RST;
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writel(val, usb2_base + USB2_USBCTR);
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val &= ~USB2_USBCTR_PLL_RST;
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writel(val, usb2_base + USB2_USBCTR);
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return 0;
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}
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static struct phy_ops rcar_gen3_phy_usb2_ops = {
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.init = rcar_gen3_phy_usb2_init,
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.exit = rcar_gen3_phy_usb2_exit,
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.power_on = rcar_gen3_phy_usb2_power_on,
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.owner = THIS_MODULE,
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};
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static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
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{
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struct rcar_gen3_chan *ch = _ch;
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void __iomem *usb2_base = ch->usb2.base;
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u32 status = readl(usb2_base + USB2_OBINTSTA);
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irqreturn_t ret = IRQ_NONE;
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if (status & USB2_OBINT_BITS) {
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dev_vdbg(&ch->phy->dev, "%s: %08x\n", __func__, status);
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writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
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rcar_gen3_device_recognition(ch);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
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{ .compatible = "renesas,usb2-phy-r8a7795" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);
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static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rcar_gen3_chan *channel;
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struct phy_provider *provider;
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struct resource *res;
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int irq;
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if (!dev->of_node) {
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dev_err(dev, "This driver needs device tree\n");
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return -EINVAL;
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}
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channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL);
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if (!channel)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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channel->usb2.base = devm_ioremap_resource(dev, res);
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if (IS_ERR(channel->usb2.base))
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return PTR_ERR(channel->usb2.base);
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/* call request_irq for OTG */
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irq = platform_get_irq(pdev, 0);
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if (irq >= 0) {
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irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
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IRQF_SHARED, dev_name(dev), channel);
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if (irq < 0)
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dev_err(dev, "No irq handler (%d)\n", irq);
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channel->has_otg = true;
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}
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/* devm_phy_create() will call pm_runtime_enable(dev); */
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channel->phy = devm_phy_create(dev, NULL, &rcar_gen3_phy_usb2_ops);
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if (IS_ERR(channel->phy)) {
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dev_err(dev, "Failed to create USB2 PHY\n");
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return PTR_ERR(channel->phy);
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}
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phy_set_drvdata(channel->phy, channel);
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(provider))
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dev_err(dev, "Failed to register PHY provider\n");
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return PTR_ERR_OR_ZERO(provider);
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}
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static struct platform_driver rcar_gen3_phy_usb2_driver = {
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.driver = {
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.name = "phy_rcar_gen3_usb2",
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.of_match_table = rcar_gen3_phy_usb2_match_table,
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},
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.probe = rcar_gen3_phy_usb2_probe,
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};
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module_platform_driver(rcar_gen3_phy_usb2_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY");
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MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
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