239 lines
9.1 KiB
C
239 lines
9.1 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _IMX_SSI_H
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#define _IMX_SSI_H
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#include <mach/hardware.h>
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/* SSI regs definition - MOVE to /arch/arm/plat-mxc/include/mach/ when stable */
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#define SSI1_IO_BASE_ADDR IO_ADDRESS(SSI1_BASE_ADDR)
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#define SSI2_IO_BASE_ADDR IO_ADDRESS(SSI2_BASE_ADDR)
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#define STX0 0x00
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#define STX1 0x04
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#define SRX0 0x08
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#define SRX1 0x0c
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#define SCR 0x10
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#define SISR 0x14
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#define SIER 0x18
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#define STCR 0x1c
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#define SRCR 0x20
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#define STCCR 0x24
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#define SRCCR 0x28
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#define SFCSR 0x2c
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#define STR 0x30
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#define SOR 0x34
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#define SACNT 0x38
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#define SACADD 0x3c
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#define SACDAT 0x40
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#define SATAG 0x44
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#define STMSK 0x48
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#define SRMSK 0x4c
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#define SSI1_STX0 (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STX0)))
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#define SSI1_STX1 (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STX1)))
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#define SSI1_SRX0 (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRX0)))
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#define SSI1_SRX1 (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRX1)))
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#define SSI1_SCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SCR)))
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#define SSI1_SISR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SISR)))
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#define SSI1_SIER (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SIER)))
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#define SSI1_STCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STCR)))
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#define SSI1_SRCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRCR)))
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#define SSI1_STCCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STCCR)))
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#define SSI1_SRCCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRCCR)))
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#define SSI1_SFCSR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SFCSR)))
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#define SSI1_STR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STR)))
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#define SSI1_SOR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SOR)))
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#define SSI1_SACNT (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SACNT)))
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#define SSI1_SACADD (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SACADD)))
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#define SSI1_SACDAT (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SACDAT)))
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#define SSI1_SATAG (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SATAG)))
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#define SSI1_STMSK (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STMSK)))
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#define SSI1_SRMSK (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRMSK)))
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#define SSI2_STX0 (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STX0)))
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#define SSI2_STX1 (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STX1)))
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#define SSI2_SRX0 (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRX0)))
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#define SSI2_SRX1 (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRX1)))
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#define SSI2_SCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SCR)))
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#define SSI2_SISR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SISR)))
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#define SSI2_SIER (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SIER)))
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#define SSI2_STCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STCR)))
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#define SSI2_SRCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRCR)))
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#define SSI2_STCCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STCCR)))
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#define SSI2_SRCCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRCCR)))
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#define SSI2_SFCSR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SFCSR)))
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#define SSI2_STR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STR)))
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#define SSI2_SOR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SOR)))
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#define SSI2_SACNT (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SACNT)))
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#define SSI2_SACADD (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SACADD)))
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#define SSI2_SACDAT (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SACDAT)))
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#define SSI2_SATAG (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SATAG)))
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#define SSI2_STMSK (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STMSK)))
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#define SSI2_SRMSK (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRMSK)))
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#define SSI_SCR_CLK_IST (1 << 9)
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#define SSI_SCR_TCH_EN (1 << 8)
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#define SSI_SCR_SYS_CLK_EN (1 << 7)
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#define SSI_SCR_I2S_MODE_NORM (0 << 5)
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#define SSI_SCR_I2S_MODE_MSTR (1 << 5)
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#define SSI_SCR_I2S_MODE_SLAVE (2 << 5)
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#define SSI_SCR_SYN (1 << 4)
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#define SSI_SCR_NET (1 << 3)
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#define SSI_SCR_RE (1 << 2)
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#define SSI_SCR_TE (1 << 1)
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#define SSI_SCR_SSIEN (1 << 0)
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#define SSI_SISR_CMDAU (1 << 18)
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#define SSI_SISR_CMDDU (1 << 17)
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#define SSI_SISR_RXT (1 << 16)
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#define SSI_SISR_RDR1 (1 << 15)
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#define SSI_SISR_RDR0 (1 << 14)
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#define SSI_SISR_TDE1 (1 << 13)
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#define SSI_SISR_TDE0 (1 << 12)
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#define SSI_SISR_ROE1 (1 << 11)
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#define SSI_SISR_ROE0 (1 << 10)
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#define SSI_SISR_TUE1 (1 << 9)
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#define SSI_SISR_TUE0 (1 << 8)
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#define SSI_SISR_TFS (1 << 7)
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#define SSI_SISR_RFS (1 << 6)
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#define SSI_SISR_TLS (1 << 5)
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#define SSI_SISR_RLS (1 << 4)
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#define SSI_SISR_RFF1 (1 << 3)
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#define SSI_SISR_RFF0 (1 << 2)
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#define SSI_SISR_TFE1 (1 << 1)
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#define SSI_SISR_TFE0 (1 << 0)
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#define SSI_SIER_RDMAE (1 << 22)
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#define SSI_SIER_RIE (1 << 21)
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#define SSI_SIER_TDMAE (1 << 20)
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#define SSI_SIER_TIE (1 << 19)
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#define SSI_SIER_CMDAU_EN (1 << 18)
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#define SSI_SIER_CMDDU_EN (1 << 17)
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#define SSI_SIER_RXT_EN (1 << 16)
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#define SSI_SIER_RDR1_EN (1 << 15)
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#define SSI_SIER_RDR0_EN (1 << 14)
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#define SSI_SIER_TDE1_EN (1 << 13)
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#define SSI_SIER_TDE0_EN (1 << 12)
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#define SSI_SIER_ROE1_EN (1 << 11)
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#define SSI_SIER_ROE0_EN (1 << 10)
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#define SSI_SIER_TUE1_EN (1 << 9)
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#define SSI_SIER_TUE0_EN (1 << 8)
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#define SSI_SIER_TFS_EN (1 << 7)
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#define SSI_SIER_RFS_EN (1 << 6)
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#define SSI_SIER_TLS_EN (1 << 5)
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#define SSI_SIER_RLS_EN (1 << 4)
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#define SSI_SIER_RFF1_EN (1 << 3)
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#define SSI_SIER_RFF0_EN (1 << 2)
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#define SSI_SIER_TFE1_EN (1 << 1)
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#define SSI_SIER_TFE0_EN (1 << 0)
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#define SSI_STCR_TXBIT0 (1 << 9)
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#define SSI_STCR_TFEN1 (1 << 8)
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#define SSI_STCR_TFEN0 (1 << 7)
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#define SSI_STCR_TFDIR (1 << 6)
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#define SSI_STCR_TXDIR (1 << 5)
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#define SSI_STCR_TSHFD (1 << 4)
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#define SSI_STCR_TSCKP (1 << 3)
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#define SSI_STCR_TFSI (1 << 2)
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#define SSI_STCR_TFSL (1 << 1)
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#define SSI_STCR_TEFS (1 << 0)
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#define SSI_SRCR_RXBIT0 (1 << 9)
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#define SSI_SRCR_RFEN1 (1 << 8)
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#define SSI_SRCR_RFEN0 (1 << 7)
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#define SSI_SRCR_RFDIR (1 << 6)
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#define SSI_SRCR_RXDIR (1 << 5)
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#define SSI_SRCR_RSHFD (1 << 4)
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#define SSI_SRCR_RSCKP (1 << 3)
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#define SSI_SRCR_RFSI (1 << 2)
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#define SSI_SRCR_RFSL (1 << 1)
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#define SSI_SRCR_REFS (1 << 0)
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#define SSI_STCCR_DIV2 (1 << 18)
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#define SSI_STCCR_PSR (1 << 15)
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#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13)
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#define SSI_STCCR_DC(x) (((x) & 0x1f) << 8)
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#define SSI_STCCR_PM(x) (((x) & 0xff) << 0)
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#define SSI_STCCR_WL_MASK (0xf << 13)
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#define SSI_STCCR_DC_MASK (0x1f << 8)
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#define SSI_STCCR_PM_MASK (0xff << 0)
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#define SSI_SRCCR_DIV2 (1 << 18)
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#define SSI_SRCCR_PSR (1 << 15)
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#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13)
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#define SSI_SRCCR_DC(x) (((x) & 0x1f) << 8)
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#define SSI_SRCCR_PM(x) (((x) & 0xff) << 0)
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#define SSI_SRCCR_WL_MASK (0xf << 13)
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#define SSI_SRCCR_DC_MASK (0x1f << 8)
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#define SSI_SRCCR_PM_MASK (0xff << 0)
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#define SSI_SFCSR_RFCNT1(x) (((x) & 0xf) << 28)
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#define SSI_SFCSR_TFCNT1(x) (((x) & 0xf) << 24)
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#define SSI_SFCSR_RFWM1(x) (((x) & 0xf) << 20)
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#define SSI_SFCSR_TFWM1(x) (((x) & 0xf) << 16)
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#define SSI_SFCSR_RFCNT0(x) (((x) & 0xf) << 12)
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#define SSI_SFCSR_TFCNT0(x) (((x) & 0xf) << 8)
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#define SSI_SFCSR_RFWM0(x) (((x) & 0xf) << 4)
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#define SSI_SFCSR_TFWM0(x) (((x) & 0xf) << 0)
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#define SSI_STR_TEST (1 << 15)
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#define SSI_STR_RCK2TCK (1 << 14)
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#define SSI_STR_RFS2TFS (1 << 13)
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#define SSI_STR_RXSTATE(x) (((x) & 0xf) << 8)
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#define SSI_STR_TXD2RXD (1 << 7)
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#define SSI_STR_TCK2RCK (1 << 6)
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#define SSI_STR_TFS2RFS (1 << 5)
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#define SSI_STR_TXSTATE(x) (((x) & 0xf) << 0)
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#define SSI_SOR_CLKOFF (1 << 6)
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#define SSI_SOR_RX_CLR (1 << 5)
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#define SSI_SOR_TX_CLR (1 << 4)
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#define SSI_SOR_INIT (1 << 3)
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#define SSI_SOR_WAIT(x) (((x) & 0x3) << 1)
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#define SSI_SOR_SYNRST (1 << 0)
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#define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
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#define SSI_SACNT_WR (x << 4)
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#define SSI_SACNT_RD (x << 3)
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#define SSI_SACNT_TIF (x << 2)
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#define SSI_SACNT_FV (x << 1)
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#define SSI_SACNT_AC97EN (x << 0)
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/* Watermarks for FIFO's */
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#define TXFIFO_WATERMARK 0x4
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#define RXFIFO_WATERMARK 0x4
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/* i.MX DAI SSP ID's */
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#define IMX_DAI_SSI0 0 /* SSI1 FIFO 0 */
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#define IMX_DAI_SSI1 1 /* SSI1 FIFO 1 */
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#define IMX_DAI_SSI2 2 /* SSI2 FIFO 0 */
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#define IMX_DAI_SSI3 3 /* SSI2 FIFO 1 */
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/* SSI clock sources */
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#define IMX_SSP_SYS_CLK 0
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/* SSI audio dividers */
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#define IMX_SSI_TX_DIV_2 0
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#define IMX_SSI_TX_DIV_PSR 1
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#define IMX_SSI_TX_DIV_PM 2
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#define IMX_SSI_RX_DIV_2 3
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#define IMX_SSI_RX_DIV_PSR 4
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#define IMX_SSI_RX_DIV_PM 5
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/* SSI Div 2 */
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#define IMX_SSI_DIV_2_OFF (~SSI_STCCR_DIV2)
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#define IMX_SSI_DIV_2_ON SSI_STCCR_DIV2
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extern struct snd_soc_dai imx_ssi_pcm_dai[4];
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extern int get_ssi_clk(int ssi, struct device *dev);
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extern void put_ssi_clk(int ssi);
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#endif
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