172 lines
5.1 KiB
C
172 lines
5.1 KiB
C
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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*/
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#ifndef _ASM_TILE_PGTABLE_64_H
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#define _ASM_TILE_PGTABLE_64_H
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/* The level-0 page table breaks the address space into 32-bit chunks. */
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#define PGDIR_SHIFT HV_LOG2_L1_SPAN
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#define PGDIR_SIZE HV_L1_SPAN
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define PTRS_PER_PGD HV_L0_ENTRIES
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#define PGD_INDEX(va) HV_L0_INDEX(va)
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#define SIZEOF_PGD HV_L0_SIZE
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/*
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* The level-1 index is defined by the huge page size. A PMD is composed
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* of PTRS_PER_PMD pgd_t's and is the middle level of the page table.
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*/
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#define PMD_SHIFT HPAGE_SHIFT
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#define PMD_SIZE HPAGE_SIZE
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PTRS_PER_PMD _HV_L1_ENTRIES(HPAGE_SHIFT)
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#define PMD_INDEX(va) _HV_L1_INDEX(va, HPAGE_SHIFT)
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#define SIZEOF_PMD _HV_L1_SIZE(HPAGE_SHIFT)
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/*
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* The level-2 index is defined by the difference between the huge
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* page size and the normal page size. A PTE is composed of
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* PTRS_PER_PTE pte_t's and is the bottom level of the page table.
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* Note that the hypervisor docs use PTE for what we call pte_t, so
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* this nomenclature is somewhat confusing.
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*/
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#define PTRS_PER_PTE _HV_L2_ENTRIES(HPAGE_SHIFT, PAGE_SHIFT)
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#define PTE_INDEX(va) _HV_L2_INDEX(va, HPAGE_SHIFT, PAGE_SHIFT)
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#define SIZEOF_PTE _HV_L2_SIZE(HPAGE_SHIFT, PAGE_SHIFT)
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/*
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* Align the vmalloc area to an L2 page table. Omit guard pages at
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* the beginning and end for simplicity (particularly in the per-cpu
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* memory allocation code). The vmalloc code puts in an internal
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* guard page between each allocation.
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*/
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#define _VMALLOC_END MEM_SV_START
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#define VMALLOC_END _VMALLOC_END
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#define VMALLOC_START _VMALLOC_START
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#ifndef __ASSEMBLY__
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/* We have no pud since we are a three-level page table. */
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#include <asm-generic/pgtable-nopud.h>
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/*
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* pmds are the same as pgds and ptes, so converting is a no-op.
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*/
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#define pmd_pte(pmd) (pmd)
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#define pmdp_ptep(pmdp) (pmdp)
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#define pte_pmd(pte) (pte)
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#define pud_pte(pud) ((pud).pgd)
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static inline int pud_none(pud_t pud)
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{
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return pud_val(pud) == 0;
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}
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static inline int pud_present(pud_t pud)
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{
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return pud_val(pud) & _PAGE_PRESENT;
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}
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static inline int pud_huge_page(pud_t pud)
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{
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return pud_val(pud) & _PAGE_HUGE_PAGE;
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}
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#define pmd_ERROR(e) \
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pr_err("%s:%d: bad pmd 0x%016llx\n", __FILE__, __LINE__, pmd_val(e))
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static inline void pud_clear(pud_t *pudp)
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{
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__pte_clear(&pudp->pgd);
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}
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static inline int pud_bad(pud_t pud)
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{
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return ((pud_val(pud) & _PAGE_ALL) != _PAGE_TABLE);
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}
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/* Return the page-table frame number (ptfn) that a pud_t points at. */
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#define pud_ptfn(pud) hv_pte_get_ptfn((pud).pgd)
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/* Return the page frame number (pfn) that a pud_t points at. */
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#define pud_pfn(pud) pte_pfn(pud_pte(pud))
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/*
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* A given kernel pud_t maps to a kernel pmd_t table at a specific
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* virtual address. Since kernel pmd_t tables can be aligned at
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* sub-page granularity, this macro can return non-page-aligned
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* pointers, despite its name.
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*/
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#define pud_page_vaddr(pud) \
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(__va((phys_addr_t)pud_ptfn(pud) << HV_LOG2_PAGE_TABLE_ALIGN))
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/*
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* A pud_t points to a pmd_t array. Since we can have multiple per
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* page, we don't have a one-to-one mapping of pud_t's to pages.
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*/
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#define pud_page(pud) pfn_to_page(PFN_DOWN(HV_PTFN_TO_CPA(pud_ptfn(pud))))
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static inline unsigned long pud_index(unsigned long address)
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{
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return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
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}
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#define pmd_offset(pud, address) \
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((pmd_t *)pud_page_vaddr(*(pud)) + pmd_index(address))
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/* Normalize an address to having the correct high bits set. */
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#define pgd_addr_normalize pgd_addr_normalize
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static inline unsigned long pgd_addr_normalize(unsigned long addr)
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{
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return ((long)addr << (CHIP_WORD_SIZE() - CHIP_VA_WIDTH())) >>
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(CHIP_WORD_SIZE() - CHIP_VA_WIDTH());
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}
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/* We don't define any pgds for these addresses. */
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static inline int pgd_addr_invalid(unsigned long addr)
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{
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return addr >= KERNEL_HIGH_VADDR || addr != pgd_addr_normalize(addr);
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}
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/*
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* Use atomic instructions to provide atomicity against the hypervisor.
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*/
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#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
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static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep)
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{
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return (__insn_fetchand(&ptep->val, ~HV_PTE_ACCESSED) >>
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HV_PTE_INDEX_ACCESSED) & 0x1;
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}
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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static inline void ptep_set_wrprotect(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep)
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{
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__insn_fetchand(&ptep->val, ~HV_PTE_WRITABLE);
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}
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
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static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep)
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{
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return hv_pte(__insn_exch(&ptep->val, 0UL));
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_TILE_PGTABLE_64_H */
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