550 lines
14 KiB
C
550 lines
14 KiB
C
/*
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* Copyright (C) 2013 BayHub Technology Ltd.
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*
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* Authors: Peter Guo <peter.guo@bayhubtech.com>
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* Adam Lee <adam.lee@canonical.com>
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* Ernest Zhang <ernest.zhang@bayhubtech.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/pci.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/delay.h>
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#include "sdhci.h"
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#include "sdhci-pci.h"
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/*
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* O2Micro device registers
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*/
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#define O2_SD_MISC_REG5 0x64
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#define O2_SD_LD0_CTRL 0x68
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#define O2_SD_DEV_CTRL 0x88
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#define O2_SD_LOCK_WP 0xD3
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#define O2_SD_TEST_REG 0xD4
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#define O2_SD_FUNC_REG0 0xDC
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#define O2_SD_MULTI_VCC3V 0xEE
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#define O2_SD_CLKREQ 0xEC
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#define O2_SD_CAPS 0xE0
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#define O2_SD_ADMA1 0xE2
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#define O2_SD_ADMA2 0xE7
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#define O2_SD_INF_MOD 0xF1
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#define O2_SD_MISC_CTRL4 0xFC
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#define O2_SD_TUNING_CTRL 0x300
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#define O2_SD_PLL_SETTING 0x304
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#define O2_SD_MISC_SETTING 0x308
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#define O2_SD_CLK_SETTING 0x328
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#define O2_SD_CAP_REG2 0x330
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#define O2_SD_CAP_REG0 0x334
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#define O2_SD_UHS1_CAP_SETTING 0x33C
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#define O2_SD_DELAY_CTRL 0x350
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#define O2_SD_UHS2_L1_CTRL 0x35C
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#define O2_SD_FUNC_REG3 0x3E0
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#define O2_SD_FUNC_REG4 0x3E4
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#define O2_SD_LED_ENABLE BIT(6)
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#define O2_SD_FREG0_LEDOFF BIT(13)
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#define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
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#define O2_SD_VENDOR_SETTING 0x110
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#define O2_SD_VENDOR_SETTING2 0x1C8
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#define O2_SD_HW_TUNING_DISABLE BIT(4)
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static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
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{
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u16 reg;
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/* enable hardware tuning */
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reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
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reg &= ~O2_SD_HW_TUNING_DISABLE;
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sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
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}
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static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
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{
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int i;
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sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200);
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for (i = 0; i < 150; i++) {
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u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
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if (ctrl & SDHCI_CTRL_TUNED_CLK) {
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host->tuning_done = true;
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return;
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}
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pr_warn("%s: HW tuning failed !\n",
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mmc_hostname(host->mmc));
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break;
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}
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mdelay(1);
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}
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pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
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mmc_hostname(host->mmc));
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sdhci_reset_tuning(host);
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}
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static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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int current_bus_width = 0;
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/*
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* This handler only implements the eMMC tuning that is specific to
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* this controller. Fall back to the standard method for other TIMING.
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*/
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if (host->timing != MMC_TIMING_MMC_HS200)
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return sdhci_execute_tuning(mmc, opcode);
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if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
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return -EINVAL;
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/*
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* o2 sdhci host didn't support 8bit emmc tuning
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*/
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if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
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current_bus_width = mmc->ios.bus_width;
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sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
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}
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sdhci_o2_set_tuning_mode(host);
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sdhci_start_tuning(host);
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__sdhci_o2_execute_tuning(host, opcode);
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sdhci_end_tuning(host);
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if (current_bus_width == MMC_BUS_WIDTH_8)
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sdhci_set_bus_width(host, current_bus_width);
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host->flags &= ~SDHCI_HS400_TUNING;
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return 0;
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}
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static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
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{
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u32 scratch_32;
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pci_read_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, &scratch_32);
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scratch_32 &= 0x0000FFFF;
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scratch_32 |= value;
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pci_write_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, scratch_32);
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}
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static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
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{
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int ret;
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u32 scratch_32;
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/* Set led of SD host function enable */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG0, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~O2_SD_FREG0_LEDOFF;
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pci_write_config_dword(chip->pdev,
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O2_SD_FUNC_REG0, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_TEST_REG, &scratch_32);
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if (ret)
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return;
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scratch_32 |= O2_SD_LED_ENABLE;
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pci_write_config_dword(chip->pdev,
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O2_SD_TEST_REG, scratch_32);
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}
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static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
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{
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u32 scratch_32;
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int ret;
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/* Improve write performance for SD3.0 */
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ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
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pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
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/* Enable Link abnormal reset generating Reset */
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ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~((1 << 19) | (1 << 11));
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scratch_32 |= (1 << 10);
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pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
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/* set card power over current protection */
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ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
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if (ret)
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return;
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scratch_32 |= (1 << 4);
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pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
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/* adjust the output delay for SD mode */
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pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
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/* Set the output voltage setting of Aux 1.2v LDO */
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ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(3 << 12);
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pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
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/* Set Max power supply capability of SD host */
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ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0x01FE);
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scratch_32 |= 0x00CC;
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pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
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/* Set DLL Tuning Window */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_TUNING_CTRL, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0x000000FF);
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scratch_32 |= 0x00000066;
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pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
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/* Set UHS2 T_EIDLE */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_UHS2_L1_CTRL, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0x000000FC);
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scratch_32 |= 0x00000084;
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pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
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/* Set UHS2 Termination */
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ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~((1 << 21) | (1 << 30));
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pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
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/* Set L1 Entrance Timer */
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ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0xf0000000);
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scratch_32 |= 0x30000000;
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pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_MISC_CTRL4, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0x000f0000);
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scratch_32 |= 0x00080000;
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pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
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}
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static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
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struct sdhci_host *host)
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{
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int ret;
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ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
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if (!ret) {
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pr_info("%s: unsupport msi, use INTx irq\n",
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mmc_hostname(host->mmc));
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return;
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}
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ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
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PCI_IRQ_MSI | PCI_IRQ_MSIX);
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if (ret < 0) {
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pr_err("%s: enable PCI MSI failed, err=%d\n",
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mmc_hostname(host->mmc), ret);
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return;
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}
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host->irq = pci_irq_vector(chip->pdev, 0);
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}
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int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
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{
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struct sdhci_pci_chip *chip;
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struct sdhci_host *host;
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u32 reg;
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int ret;
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chip = slot->chip;
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host = slot->host;
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switch (chip->pdev->device) {
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case PCI_DEVICE_ID_O2_SDS0:
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case PCI_DEVICE_ID_O2_SEABIRD0:
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case PCI_DEVICE_ID_O2_SEABIRD1:
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case PCI_DEVICE_ID_O2_SDS1:
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case PCI_DEVICE_ID_O2_FUJIN2:
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reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
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if (reg & 0x1)
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host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
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sdhci_pci_o2_enable_msi(chip, host);
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if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_MISC_SETTING, ®);
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if (ret)
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return -EIO;
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if (reg & (1 << 4)) {
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pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
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mmc_hostname(host->mmc));
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host->flags &= ~SDHCI_SIGNALING_330;
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host->flags |= SDHCI_SIGNALING_180;
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host->mmc->caps2 |= MMC_CAP2_NO_SD;
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host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
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}
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}
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host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
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if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
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break;
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/* set dll watch dog timer */
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reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
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reg |= (1 << 12);
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sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
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break;
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default:
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break;
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}
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return 0;
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}
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int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
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{
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int ret;
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u8 scratch;
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u32 scratch_32;
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switch (chip->pdev->device) {
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case PCI_DEVICE_ID_O2_8220:
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case PCI_DEVICE_ID_O2_8221:
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case PCI_DEVICE_ID_O2_8320:
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case PCI_DEVICE_ID_O2_8321:
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/* This extra setup is required due to broken ADMA. */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch &= 0x7f;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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/* Set Multi 3 to VCC3V# */
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pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
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/* Disable CLK_REQ# support after media DET */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_CLKREQ, &scratch);
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if (ret)
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return ret;
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scratch |= 0x20;
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pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
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/* Choose capabilities, enable SDMA. We have to write 0x01
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* to the capabilities register first to unlock it.
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*/
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ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
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if (ret)
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return ret;
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scratch |= 0x01;
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pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
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pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
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/* Disable ADMA1/2 */
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pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
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pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
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/* Disable the infinite transfer mode */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_INF_MOD, &scratch);
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if (ret)
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return ret;
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scratch |= 0x08;
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pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
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/* Lock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch |= 0x80;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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break;
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case PCI_DEVICE_ID_O2_SDS0:
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case PCI_DEVICE_ID_O2_SDS1:
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case PCI_DEVICE_ID_O2_FUJIN2:
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/* UnLock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch &= 0x7f;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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/* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
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if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG0,
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&scratch_32);
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scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
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/* Check Whether subId is 0x11 or 0x12 */
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if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
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scratch_32 = 0x25100000;
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o2_pci_set_baseclk(chip, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG4,
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&scratch_32);
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/* Enable Base Clk setting change */
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scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
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pci_write_config_dword(chip->pdev,
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O2_SD_FUNC_REG4,
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scratch_32);
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/* Set Tuning Window to 4 */
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pci_write_config_byte(chip->pdev,
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O2_SD_TUNING_CTRL, 0x44);
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break;
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}
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}
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/* Enable 8520 led function */
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o2_pci_led_enable(chip);
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/* Set timeout CLK */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_CLK_SETTING, &scratch_32);
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if (ret)
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return ret;
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scratch_32 &= ~(0xFF00);
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scratch_32 |= 0x07E0C800;
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pci_write_config_dword(chip->pdev,
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O2_SD_CLK_SETTING, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_CLKREQ, &scratch_32);
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if (ret)
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return ret;
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scratch_32 |= 0x3;
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pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, &scratch_32);
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if (ret)
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return ret;
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scratch_32 &= ~(0x1F3F070E);
|
|
scratch_32 |= 0x18270106;
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_PLL_SETTING, scratch_32);
|
|
|
|
/* Disable UHS1 funciton */
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_CAP_REG2, &scratch_32);
|
|
if (ret)
|
|
return ret;
|
|
scratch_32 &= ~(0xE0);
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_CAP_REG2, scratch_32);
|
|
|
|
if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
|
|
sdhci_pci_o2_fujin2_pci_init(chip);
|
|
|
|
/* Lock WP */
|
|
ret = pci_read_config_byte(chip->pdev,
|
|
O2_SD_LOCK_WP, &scratch);
|
|
if (ret)
|
|
return ret;
|
|
scratch |= 0x80;
|
|
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
|
break;
|
|
case PCI_DEVICE_ID_O2_SEABIRD0:
|
|
case PCI_DEVICE_ID_O2_SEABIRD1:
|
|
/* UnLock WP */
|
|
ret = pci_read_config_byte(chip->pdev,
|
|
O2_SD_LOCK_WP, &scratch);
|
|
if (ret)
|
|
return ret;
|
|
|
|
scratch &= 0x7f;
|
|
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
|
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_PLL_SETTING, &scratch_32);
|
|
|
|
if ((scratch_32 & 0xff000000) == 0x01000000) {
|
|
scratch_32 &= 0x0000FFFF;
|
|
scratch_32 |= 0x1F340000;
|
|
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_PLL_SETTING, scratch_32);
|
|
} else {
|
|
scratch_32 &= 0x0000FFFF;
|
|
scratch_32 |= 0x25100000;
|
|
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_PLL_SETTING, scratch_32);
|
|
|
|
ret = pci_read_config_dword(chip->pdev,
|
|
O2_SD_FUNC_REG4,
|
|
&scratch_32);
|
|
scratch_32 |= (1 << 22);
|
|
pci_write_config_dword(chip->pdev,
|
|
O2_SD_FUNC_REG4, scratch_32);
|
|
}
|
|
|
|
/* Set Tuning Windows to 5 */
|
|
pci_write_config_byte(chip->pdev,
|
|
O2_SD_TUNING_CTRL, 0x55);
|
|
/* Lock WP */
|
|
ret = pci_read_config_byte(chip->pdev,
|
|
O2_SD_LOCK_WP, &scratch);
|
|
if (ret)
|
|
return ret;
|
|
scratch |= 0x80;
|
|
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
|
|
{
|
|
sdhci_pci_o2_probe(chip);
|
|
return sdhci_pci_resume_host(chip);
|
|
}
|
|
#endif
|