1015 lines
23 KiB
C
1015 lines
23 KiB
C
/*
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* Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
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* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <linux/module.h>
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#include <linux/export.h>
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#include <linux/types.h>
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#include <linux/reset.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/list.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_device.h>
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#include <drm/drm_fourcc.h>
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#include <video/imx-ipu-v3.h>
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#include "ipu-prv.h"
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static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
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{
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return readl(ipu->cm_reg + offset);
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}
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static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
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{
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writel(value, ipu->cm_reg + offset);
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}
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void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
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{
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u32 val;
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val = ipu_cm_read(ipu, IPU_SRM_PRI2);
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val |= 0x8;
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ipu_cm_write(ipu, val, IPU_SRM_PRI2);
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}
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EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
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enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
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{
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switch (drm_fourcc) {
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case DRM_FORMAT_RGB565:
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case DRM_FORMAT_BGR565:
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case DRM_FORMAT_RGB888:
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case DRM_FORMAT_BGR888:
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_RGBX8888:
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case DRM_FORMAT_BGRX8888:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_RGBA8888:
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case DRM_FORMAT_BGRA8888:
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return IPUV3_COLORSPACE_RGB;
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case DRM_FORMAT_YUYV:
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case DRM_FORMAT_UYVY:
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case DRM_FORMAT_YUV420:
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case DRM_FORMAT_YVU420:
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return IPUV3_COLORSPACE_YUV;
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default:
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return IPUV3_COLORSPACE_UNKNOWN;
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}
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}
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EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
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enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
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{
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switch (pixelformat) {
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case V4L2_PIX_FMT_YUV420:
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case V4L2_PIX_FMT_YVU420:
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case V4L2_PIX_FMT_UYVY:
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case V4L2_PIX_FMT_YUYV:
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return IPUV3_COLORSPACE_YUV;
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case V4L2_PIX_FMT_RGB32:
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case V4L2_PIX_FMT_BGR32:
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case V4L2_PIX_FMT_RGB24:
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case V4L2_PIX_FMT_BGR24:
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case V4L2_PIX_FMT_RGB565:
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return IPUV3_COLORSPACE_RGB;
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default:
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return IPUV3_COLORSPACE_UNKNOWN;
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}
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}
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EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
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enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
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{
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switch (mbus_code & 0xf000) {
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case 0x1000:
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return IPUV3_COLORSPACE_RGB;
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case 0x2000:
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return IPUV3_COLORSPACE_YUV;
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default:
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return IPUV3_COLORSPACE_UNKNOWN;
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}
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}
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EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
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struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
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{
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struct ipuv3_channel *channel;
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dev_dbg(ipu->dev, "%s %d\n", __func__, num);
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if (num > 63)
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return ERR_PTR(-ENODEV);
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mutex_lock(&ipu->channel_lock);
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channel = &ipu->channel[num];
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if (channel->busy) {
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channel = ERR_PTR(-EBUSY);
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goto out;
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}
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channel->busy = true;
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channel->num = num;
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out:
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mutex_unlock(&ipu->channel_lock);
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return channel;
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_get);
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void ipu_idmac_put(struct ipuv3_channel *channel)
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{
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struct ipu_soc *ipu = channel->ipu;
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dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
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mutex_lock(&ipu->channel_lock);
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channel->busy = false;
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mutex_unlock(&ipu->channel_lock);
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_put);
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#define idma_mask(ch) (1 << (ch & 0x1f))
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void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
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bool doublebuffer)
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{
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struct ipu_soc *ipu = channel->ipu;
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&ipu->lock, flags);
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reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
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if (doublebuffer)
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reg |= idma_mask(channel->num);
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else
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reg &= ~idma_mask(channel->num);
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ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
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spin_unlock_irqrestore(&ipu->lock, flags);
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
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int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
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{
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unsigned long lock_flags;
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u32 val;
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spin_lock_irqsave(&ipu->lock, lock_flags);
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val = ipu_cm_read(ipu, IPU_DISP_GEN);
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if (mask & IPU_CONF_DI0_EN)
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val |= IPU_DI0_COUNTER_RELEASE;
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if (mask & IPU_CONF_DI1_EN)
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val |= IPU_DI1_COUNTER_RELEASE;
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ipu_cm_write(ipu, val, IPU_DISP_GEN);
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val = ipu_cm_read(ipu, IPU_CONF);
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val |= mask;
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ipu_cm_write(ipu, val, IPU_CONF);
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spin_unlock_irqrestore(&ipu->lock, lock_flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_module_enable);
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int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
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{
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unsigned long lock_flags;
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u32 val;
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spin_lock_irqsave(&ipu->lock, lock_flags);
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val = ipu_cm_read(ipu, IPU_CONF);
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val &= ~mask;
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ipu_cm_write(ipu, val, IPU_CONF);
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val = ipu_cm_read(ipu, IPU_DISP_GEN);
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if (mask & IPU_CONF_DI0_EN)
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val &= ~IPU_DI0_COUNTER_RELEASE;
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if (mask & IPU_CONF_DI1_EN)
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val &= ~IPU_DI1_COUNTER_RELEASE;
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ipu_cm_write(ipu, val, IPU_DISP_GEN);
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spin_unlock_irqrestore(&ipu->lock, lock_flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_module_disable);
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int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
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{
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struct ipu_soc *ipu = channel->ipu;
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unsigned int chno = channel->num;
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return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
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void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
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{
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struct ipu_soc *ipu = channel->ipu;
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unsigned int chno = channel->num;
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unsigned long flags;
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spin_lock_irqsave(&ipu->lock, flags);
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/* Mark buffer as ready. */
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if (buf_num == 0)
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ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
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else
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ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
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spin_unlock_irqrestore(&ipu->lock, flags);
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
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int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
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{
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struct ipu_soc *ipu = channel->ipu;
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u32 val;
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unsigned long flags;
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spin_lock_irqsave(&ipu->lock, flags);
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val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
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val |= idma_mask(channel->num);
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ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
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spin_unlock_irqrestore(&ipu->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
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bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
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{
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return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
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int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
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{
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struct ipu_soc *ipu = channel->ipu;
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unsigned long timeout;
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timeout = jiffies + msecs_to_jiffies(ms);
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while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
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idma_mask(channel->num)) {
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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cpu_relax();
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
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int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
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{
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unsigned long timeout;
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timeout = jiffies + msecs_to_jiffies(ms);
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ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
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while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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cpu_relax();
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
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int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
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{
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struct ipu_soc *ipu = channel->ipu;
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u32 val;
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unsigned long flags;
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spin_lock_irqsave(&ipu->lock, flags);
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/* Disable DMA channel(s) */
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val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
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val &= ~idma_mask(channel->num);
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ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
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/* Set channel buffers NOT to be ready */
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ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
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if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
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idma_mask(channel->num)) {
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ipu_cm_write(ipu, idma_mask(channel->num),
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IPU_CHA_BUF0_RDY(channel->num));
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}
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if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
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idma_mask(channel->num)) {
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ipu_cm_write(ipu, idma_mask(channel->num),
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IPU_CHA_BUF1_RDY(channel->num));
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}
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ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
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/* Reset the double buffer */
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val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
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val &= ~idma_mask(channel->num);
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ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
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spin_unlock_irqrestore(&ipu->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
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static int ipu_memory_reset(struct ipu_soc *ipu)
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{
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unsigned long timeout;
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ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
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timeout = jiffies + msecs_to_jiffies(1000);
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while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
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if (time_after(jiffies, timeout))
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return -ETIME;
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cpu_relax();
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}
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return 0;
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}
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/*
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* Set the source mux for the given CSI. Selects either parallel or
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* MIPI CSI2 sources.
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*/
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void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
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{
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unsigned long flags;
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u32 val, mask;
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mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
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IPU_CONF_CSI0_DATA_SOURCE;
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spin_lock_irqsave(&ipu->lock, flags);
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val = ipu_cm_read(ipu, IPU_CONF);
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if (mipi_csi2)
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val |= mask;
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else
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val &= ~mask;
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ipu_cm_write(ipu, val, IPU_CONF);
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spin_unlock_irqrestore(&ipu->lock, flags);
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}
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EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
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/*
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* Set the source mux for the IC. Selects either CSI[01] or the VDI.
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*/
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void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&ipu->lock, flags);
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val = ipu_cm_read(ipu, IPU_CONF);
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if (vdi) {
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val |= IPU_CONF_IC_INPUT;
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} else {
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val &= ~IPU_CONF_IC_INPUT;
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if (csi_id == 1)
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val |= IPU_CONF_CSI_SEL;
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else
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val &= ~IPU_CONF_CSI_SEL;
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}
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ipu_cm_write(ipu, val, IPU_CONF);
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spin_unlock_irqrestore(&ipu->lock, flags);
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}
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EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
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struct ipu_devtype {
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const char *name;
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unsigned long cm_ofs;
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unsigned long cpmem_ofs;
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unsigned long srm_ofs;
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unsigned long tpm_ofs;
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unsigned long csi0_ofs;
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unsigned long csi1_ofs;
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unsigned long ic_ofs;
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unsigned long disp0_ofs;
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unsigned long disp1_ofs;
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unsigned long dc_tmpl_ofs;
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unsigned long vdi_ofs;
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enum ipuv3_type type;
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};
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static struct ipu_devtype ipu_type_imx51 = {
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.name = "IPUv3EX",
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.cm_ofs = 0x1e000000,
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.cpmem_ofs = 0x1f000000,
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.srm_ofs = 0x1f040000,
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.tpm_ofs = 0x1f060000,
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.csi0_ofs = 0x1f030000,
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.csi1_ofs = 0x1f038000,
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.ic_ofs = 0x1f020000,
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.disp0_ofs = 0x1e040000,
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.disp1_ofs = 0x1e048000,
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.dc_tmpl_ofs = 0x1f080000,
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.vdi_ofs = 0x1e068000,
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.type = IPUV3EX,
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};
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static struct ipu_devtype ipu_type_imx53 = {
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.name = "IPUv3M",
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.cm_ofs = 0x06000000,
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.cpmem_ofs = 0x07000000,
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.srm_ofs = 0x07040000,
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.tpm_ofs = 0x07060000,
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.csi0_ofs = 0x07030000,
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.csi1_ofs = 0x07038000,
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.ic_ofs = 0x07020000,
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.disp0_ofs = 0x06040000,
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.disp1_ofs = 0x06048000,
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.dc_tmpl_ofs = 0x07080000,
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.vdi_ofs = 0x06068000,
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.type = IPUV3M,
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};
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static struct ipu_devtype ipu_type_imx6q = {
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.name = "IPUv3H",
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.cm_ofs = 0x00200000,
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.cpmem_ofs = 0x00300000,
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.srm_ofs = 0x00340000,
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.tpm_ofs = 0x00360000,
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.csi0_ofs = 0x00230000,
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.csi1_ofs = 0x00238000,
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.ic_ofs = 0x00220000,
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.disp0_ofs = 0x00240000,
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.disp1_ofs = 0x00248000,
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.dc_tmpl_ofs = 0x00380000,
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.vdi_ofs = 0x00268000,
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.type = IPUV3H,
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};
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static const struct of_device_id imx_ipu_dt_ids[] = {
|
|
{ .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
|
|
{ .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
|
|
{ .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
|
|
|
|
static int ipu_submodules_init(struct ipu_soc *ipu,
|
|
struct platform_device *pdev, unsigned long ipu_base,
|
|
struct clk *ipu_clk)
|
|
{
|
|
char *unit;
|
|
int ret;
|
|
struct device *dev = &pdev->dev;
|
|
const struct ipu_devtype *devtype = ipu->devtype;
|
|
|
|
ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
|
|
if (ret) {
|
|
unit = "cpmem";
|
|
goto err_cpmem;
|
|
}
|
|
|
|
ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
|
|
IPU_CONF_CSI0_EN, ipu_clk);
|
|
if (ret) {
|
|
unit = "csi0";
|
|
goto err_csi_0;
|
|
}
|
|
|
|
ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
|
|
IPU_CONF_CSI1_EN, ipu_clk);
|
|
if (ret) {
|
|
unit = "csi1";
|
|
goto err_csi_1;
|
|
}
|
|
|
|
ret = ipu_ic_init(ipu, dev,
|
|
ipu_base + devtype->ic_ofs,
|
|
ipu_base + devtype->tpm_ofs);
|
|
if (ret) {
|
|
unit = "ic";
|
|
goto err_ic;
|
|
}
|
|
|
|
ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
|
|
IPU_CONF_DI0_EN, ipu_clk);
|
|
if (ret) {
|
|
unit = "di0";
|
|
goto err_di_0;
|
|
}
|
|
|
|
ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
|
|
IPU_CONF_DI1_EN, ipu_clk);
|
|
if (ret) {
|
|
unit = "di1";
|
|
goto err_di_1;
|
|
}
|
|
|
|
ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
|
|
IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
|
|
if (ret) {
|
|
unit = "dc_template";
|
|
goto err_dc;
|
|
}
|
|
|
|
ret = ipu_dmfc_init(ipu, dev, ipu_base +
|
|
devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
|
|
if (ret) {
|
|
unit = "dmfc";
|
|
goto err_dmfc;
|
|
}
|
|
|
|
ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
|
|
if (ret) {
|
|
unit = "dp";
|
|
goto err_dp;
|
|
}
|
|
|
|
ret = ipu_smfc_init(ipu, dev, ipu_base +
|
|
devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
|
|
if (ret) {
|
|
unit = "smfc";
|
|
goto err_smfc;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_smfc:
|
|
ipu_dp_exit(ipu);
|
|
err_dp:
|
|
ipu_dmfc_exit(ipu);
|
|
err_dmfc:
|
|
ipu_dc_exit(ipu);
|
|
err_dc:
|
|
ipu_di_exit(ipu, 1);
|
|
err_di_1:
|
|
ipu_di_exit(ipu, 0);
|
|
err_di_0:
|
|
ipu_ic_exit(ipu);
|
|
err_ic:
|
|
ipu_csi_exit(ipu, 1);
|
|
err_csi_1:
|
|
ipu_csi_exit(ipu, 0);
|
|
err_csi_0:
|
|
ipu_cpmem_exit(ipu);
|
|
err_cpmem:
|
|
dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
|
|
return ret;
|
|
}
|
|
|
|
static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
|
|
{
|
|
unsigned long status;
|
|
int i, bit, irq;
|
|
|
|
for (i = 0; i < num_regs; i++) {
|
|
|
|
status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
|
|
status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
|
|
|
|
for_each_set_bit(bit, &status, 32) {
|
|
irq = irq_linear_revmap(ipu->domain,
|
|
regs[i] * 32 + bit);
|
|
if (irq)
|
|
generic_handle_irq(irq);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|
{
|
|
struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
|
|
const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
|
|
struct irq_chip *chip = irq_get_chip(irq);
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|
{
|
|
struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
|
|
const int int_reg[] = { 4, 5, 8, 9};
|
|
struct irq_chip *chip = irq_get_chip(irq);
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
int ipu_map_irq(struct ipu_soc *ipu, int irq)
|
|
{
|
|
int virq;
|
|
|
|
virq = irq_linear_revmap(ipu->domain, irq);
|
|
if (!virq)
|
|
virq = irq_create_mapping(ipu->domain, irq);
|
|
|
|
return virq;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_map_irq);
|
|
|
|
int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
|
|
enum ipu_channel_irq irq_type)
|
|
{
|
|
return ipu_map_irq(ipu, irq_type + channel->num);
|
|
}
|
|
EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
|
|
|
|
static void ipu_submodules_exit(struct ipu_soc *ipu)
|
|
{
|
|
ipu_smfc_exit(ipu);
|
|
ipu_dp_exit(ipu);
|
|
ipu_dmfc_exit(ipu);
|
|
ipu_dc_exit(ipu);
|
|
ipu_di_exit(ipu, 1);
|
|
ipu_di_exit(ipu, 0);
|
|
ipu_ic_exit(ipu);
|
|
ipu_csi_exit(ipu, 1);
|
|
ipu_csi_exit(ipu, 0);
|
|
ipu_cpmem_exit(ipu);
|
|
}
|
|
|
|
static int platform_remove_devices_fn(struct device *dev, void *unused)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
platform_device_unregister(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void platform_device_unregister_children(struct platform_device *pdev)
|
|
{
|
|
device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
|
|
}
|
|
|
|
struct ipu_platform_reg {
|
|
struct ipu_client_platformdata pdata;
|
|
const char *name;
|
|
int reg_offset;
|
|
};
|
|
|
|
static const struct ipu_platform_reg client_reg[] = {
|
|
{
|
|
.pdata = {
|
|
.di = 0,
|
|
.dc = 5,
|
|
.dp = IPU_DP_FLOW_SYNC_BG,
|
|
.dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
|
|
.dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
|
|
},
|
|
.name = "imx-ipuv3-crtc",
|
|
}, {
|
|
.pdata = {
|
|
.di = 1,
|
|
.dc = 1,
|
|
.dp = -EINVAL,
|
|
.dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
|
|
.dma[1] = -EINVAL,
|
|
},
|
|
.name = "imx-ipuv3-crtc",
|
|
}, {
|
|
.pdata = {
|
|
.csi = 0,
|
|
.dma[0] = IPUV3_CHANNEL_CSI0,
|
|
.dma[1] = -EINVAL,
|
|
},
|
|
.reg_offset = IPU_CM_CSI0_REG_OFS,
|
|
.name = "imx-ipuv3-camera",
|
|
}, {
|
|
.pdata = {
|
|
.csi = 1,
|
|
.dma[0] = IPUV3_CHANNEL_CSI1,
|
|
.dma[1] = -EINVAL,
|
|
},
|
|
.reg_offset = IPU_CM_CSI1_REG_OFS,
|
|
.name = "imx-ipuv3-camera",
|
|
},
|
|
};
|
|
|
|
static DEFINE_MUTEX(ipu_client_id_mutex);
|
|
static int ipu_client_id;
|
|
|
|
static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
|
|
{
|
|
struct device *dev = ipu->dev;
|
|
unsigned i;
|
|
int id, ret;
|
|
|
|
mutex_lock(&ipu_client_id_mutex);
|
|
id = ipu_client_id;
|
|
ipu_client_id += ARRAY_SIZE(client_reg);
|
|
mutex_unlock(&ipu_client_id_mutex);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
|
|
const struct ipu_platform_reg *reg = &client_reg[i];
|
|
struct platform_device *pdev;
|
|
struct resource res;
|
|
|
|
if (reg->reg_offset) {
|
|
memset(&res, 0, sizeof(res));
|
|
res.flags = IORESOURCE_MEM;
|
|
res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset;
|
|
res.end = res.start + PAGE_SIZE - 1;
|
|
pdev = platform_device_register_resndata(dev, reg->name,
|
|
id++, &res, 1, ®->pdata, sizeof(reg->pdata));
|
|
} else {
|
|
pdev = platform_device_register_data(dev, reg->name,
|
|
id++, ®->pdata, sizeof(reg->pdata));
|
|
}
|
|
|
|
if (IS_ERR(pdev))
|
|
goto err_register;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_register:
|
|
platform_device_unregister_children(to_platform_device(dev));
|
|
|
|
return ret;
|
|
}
|
|
|
|
|
|
static int ipu_irq_init(struct ipu_soc *ipu)
|
|
{
|
|
struct irq_chip_generic *gc;
|
|
struct irq_chip_type *ct;
|
|
unsigned long unused[IPU_NUM_IRQS / 32] = {
|
|
0x400100d0, 0xffe000fd,
|
|
0x400100d0, 0xffe000fd,
|
|
0x400100d0, 0xffe000fd,
|
|
0x4077ffff, 0xffe7e1fd,
|
|
0x23fffffe, 0x8880fff0,
|
|
0xf98fe7d0, 0xfff81fff,
|
|
0x400100d0, 0xffe000fd,
|
|
0x00000000,
|
|
};
|
|
int ret, i;
|
|
|
|
ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
|
|
&irq_generic_chip_ops, ipu);
|
|
if (!ipu->domain) {
|
|
dev_err(ipu->dev, "failed to add irq domain\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
|
|
handle_level_irq, 0,
|
|
IRQF_VALID, 0);
|
|
if (ret < 0) {
|
|
dev_err(ipu->dev, "failed to alloc generic irq chips\n");
|
|
irq_domain_remove(ipu->domain);
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < IPU_NUM_IRQS; i += 32) {
|
|
gc = irq_get_domain_generic_chip(ipu->domain, i);
|
|
gc->reg_base = ipu->cm_reg;
|
|
gc->unused = unused[i / 32];
|
|
ct = gc->chip_types;
|
|
ct->chip.irq_ack = irq_gc_ack_set_bit;
|
|
ct->chip.irq_mask = irq_gc_mask_clr_bit;
|
|
ct->chip.irq_unmask = irq_gc_mask_set_bit;
|
|
ct->regs.ack = IPU_INT_STAT(i / 32);
|
|
ct->regs.mask = IPU_INT_CTRL(i / 32);
|
|
}
|
|
|
|
irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
|
|
irq_set_handler_data(ipu->irq_sync, ipu);
|
|
irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
|
|
irq_set_handler_data(ipu->irq_err, ipu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ipu_irq_exit(struct ipu_soc *ipu)
|
|
{
|
|
int i, irq;
|
|
|
|
irq_set_chained_handler(ipu->irq_err, NULL);
|
|
irq_set_handler_data(ipu->irq_err, NULL);
|
|
irq_set_chained_handler(ipu->irq_sync, NULL);
|
|
irq_set_handler_data(ipu->irq_sync, NULL);
|
|
|
|
/* TODO: remove irq_domain_generic_chips */
|
|
|
|
for (i = 0; i < IPU_NUM_IRQS; i++) {
|
|
irq = irq_linear_revmap(ipu->domain, i);
|
|
if (irq)
|
|
irq_dispose_mapping(irq);
|
|
}
|
|
|
|
irq_domain_remove(ipu->domain);
|
|
}
|
|
|
|
static int ipu_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *of_id =
|
|
of_match_device(imx_ipu_dt_ids, &pdev->dev);
|
|
struct ipu_soc *ipu;
|
|
struct resource *res;
|
|
unsigned long ipu_base;
|
|
int i, ret, irq_sync, irq_err;
|
|
const struct ipu_devtype *devtype;
|
|
|
|
devtype = of_id->data;
|
|
|
|
irq_sync = platform_get_irq(pdev, 0);
|
|
irq_err = platform_get_irq(pdev, 1);
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
|
|
irq_sync, irq_err);
|
|
|
|
if (!res || irq_sync < 0 || irq_err < 0)
|
|
return -ENODEV;
|
|
|
|
ipu_base = res->start;
|
|
|
|
ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
|
|
if (!ipu)
|
|
return -ENODEV;
|
|
|
|
for (i = 0; i < 64; i++)
|
|
ipu->channel[i].ipu = ipu;
|
|
ipu->devtype = devtype;
|
|
ipu->ipu_type = devtype->type;
|
|
|
|
spin_lock_init(&ipu->lock);
|
|
mutex_init(&ipu->channel_lock);
|
|
|
|
dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
|
|
ipu_base + devtype->cm_ofs);
|
|
dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
|
|
ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
|
|
dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
|
|
ipu_base + devtype->cpmem_ofs);
|
|
dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
|
|
ipu_base + devtype->csi0_ofs);
|
|
dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
|
|
ipu_base + devtype->csi1_ofs);
|
|
dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
|
|
ipu_base + devtype->ic_ofs);
|
|
dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
|
|
ipu_base + devtype->disp0_ofs);
|
|
dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
|
|
ipu_base + devtype->disp1_ofs);
|
|
dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
|
|
ipu_base + devtype->srm_ofs);
|
|
dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
|
|
ipu_base + devtype->tpm_ofs);
|
|
dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
|
|
ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
|
|
dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
|
|
ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
|
|
dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
|
|
ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
|
|
dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
|
|
ipu_base + devtype->vdi_ofs);
|
|
|
|
ipu->cm_reg = devm_ioremap(&pdev->dev,
|
|
ipu_base + devtype->cm_ofs, PAGE_SIZE);
|
|
ipu->idmac_reg = devm_ioremap(&pdev->dev,
|
|
ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
|
|
PAGE_SIZE);
|
|
|
|
if (!ipu->cm_reg || !ipu->idmac_reg)
|
|
return -ENOMEM;
|
|
|
|
ipu->clk = devm_clk_get(&pdev->dev, "bus");
|
|
if (IS_ERR(ipu->clk)) {
|
|
ret = PTR_ERR(ipu->clk);
|
|
dev_err(&pdev->dev, "clk_get failed with %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, ipu);
|
|
|
|
ret = clk_prepare_enable(ipu->clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ipu->dev = &pdev->dev;
|
|
ipu->irq_sync = irq_sync;
|
|
ipu->irq_err = irq_err;
|
|
|
|
ret = ipu_irq_init(ipu);
|
|
if (ret)
|
|
goto out_failed_irq;
|
|
|
|
ret = device_reset(&pdev->dev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to reset: %d\n", ret);
|
|
goto out_failed_reset;
|
|
}
|
|
ret = ipu_memory_reset(ipu);
|
|
if (ret)
|
|
goto out_failed_reset;
|
|
|
|
/* Set MCU_T to divide MCU access window into 2 */
|
|
ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
|
|
IPU_DISP_GEN);
|
|
|
|
ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
|
|
if (ret)
|
|
goto failed_submodules_init;
|
|
|
|
ret = ipu_add_client_devices(ipu, ipu_base);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "adding client devices failed with %d\n",
|
|
ret);
|
|
goto failed_add_clients;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "%s probed\n", devtype->name);
|
|
|
|
return 0;
|
|
|
|
failed_add_clients:
|
|
ipu_submodules_exit(ipu);
|
|
failed_submodules_init:
|
|
out_failed_reset:
|
|
ipu_irq_exit(ipu);
|
|
out_failed_irq:
|
|
clk_disable_unprepare(ipu->clk);
|
|
return ret;
|
|
}
|
|
|
|
static int ipu_remove(struct platform_device *pdev)
|
|
{
|
|
struct ipu_soc *ipu = platform_get_drvdata(pdev);
|
|
|
|
platform_device_unregister_children(pdev);
|
|
ipu_submodules_exit(ipu);
|
|
ipu_irq_exit(ipu);
|
|
|
|
clk_disable_unprepare(ipu->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver imx_ipu_driver = {
|
|
.driver = {
|
|
.name = "imx-ipuv3",
|
|
.of_match_table = imx_ipu_dt_ids,
|
|
},
|
|
.probe = ipu_probe,
|
|
.remove = ipu_remove,
|
|
};
|
|
|
|
module_platform_driver(imx_ipu_driver);
|
|
|
|
MODULE_ALIAS("platform:imx-ipuv3");
|
|
MODULE_DESCRIPTION("i.MX IPU v3 driver");
|
|
MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
|
|
MODULE_LICENSE("GPL");
|