Leif Lindholm 86c8b27a01 arm64: ignore DT memreserve entries when booting in UEFI mode ... UEFI provides its own method for marking regions to reserve, via the memory map which is also used to initialise memblock. So when using the UEFI memory map, ignore any memreserve entries present in the DT. Reported-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>		2014-08-19 20:22:03 +01:00
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Makefile	arm64: mm: Optimise tlb flush logic where we have >4K granule	2014-05-09 17:00:48 +01:00
cache.S	arm64: mm: use inner-shareable barriers for inner-shareable maintenance	2014-05-09 17:21:24 +01:00
context.c	arm64: Process management	2012-09-17 13:41:58 +01:00
copypage.c	arm64: export __cpu_{clear,copy}_user_page functions	2014-07-08 17:30:51 +01:00
dma-mapping.c	arm64: Clean up the default pgprot setting	2014-05-09 15:53:37 +01:00
extable.c	arm64: MMU fault handling and page table management	2012-09-17 13:41:57 +01:00
fault.c	arm64: mm: Implement 4 levels of translation tables	2014-07-23 15:27:40 +01:00
flush.c	arm64: mm: Make icache synchronisation logic huge page aware	2014-07-04 14:26:01 +01:00
hugetlbpage.c	hugetlb: restrict hugepage_migration_support() to x86_64	2014-06-04 16:53:51 -07:00
init.c	arm64: ignore DT memreserve entries when booting in UEFI mode	2014-08-19 20:22:03 +01:00
ioremap.c	arm64: Convert bool ARM64_x_LEVELS to int ARM64_PGTABLE_LEVELS	2014-07-23 15:27:46 +01:00
mm.h	arm64: Remove __flush_dcache_page()	2013-06-07 17:58:30 +01:00
mmap.c	mm: remove free_area_cache	2013-07-10 18:11:34 -07:00
mmu.c	arm64: mm: Implement 4 levels of translation tables	2014-07-23 15:27:40 +01:00
pgd.c	arm64: simplify pgd_alloc	2014-02-05 10:45:07 +00:00
proc-macros.S	arm64: mm: use ubfm for dcache_line_size	2014-01-22 16:23:58 +00:00
proc.S	arm64: mm: use inner-shareable barriers for inner-shareable maintenance	2014-05-09 17:21:24 +01:00