1080 lines
26 KiB
C
1080 lines
26 KiB
C
/*
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* OMAP2 McSPI controller driver
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*
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* Copyright (C) 2005, 2006 Nokia Corporation
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* Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
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* Juha Yrjölä <juha.yrjola@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/spi/spi.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/clock.h>
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#define OMAP2_MCSPI_MAX_FREQ 48000000
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#define OMAP2_MCSPI_REVISION 0x00
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#define OMAP2_MCSPI_SYSCONFIG 0x10
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#define OMAP2_MCSPI_SYSSTATUS 0x14
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#define OMAP2_MCSPI_IRQSTATUS 0x18
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#define OMAP2_MCSPI_IRQENABLE 0x1c
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#define OMAP2_MCSPI_WAKEUPENABLE 0x20
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#define OMAP2_MCSPI_SYST 0x24
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#define OMAP2_MCSPI_MODULCTRL 0x28
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/* per-channel banks, 0x14 bytes each, first is: */
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#define OMAP2_MCSPI_CHCONF0 0x2c
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#define OMAP2_MCSPI_CHSTAT0 0x30
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#define OMAP2_MCSPI_CHCTRL0 0x34
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#define OMAP2_MCSPI_TX0 0x38
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#define OMAP2_MCSPI_RX0 0x3c
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/* per-register bitmasks: */
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#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
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#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
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#define OMAP2_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
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#define OMAP2_MCSPI_MODULCTRL_SINGLE (1 << 0)
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#define OMAP2_MCSPI_MODULCTRL_MS (1 << 2)
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#define OMAP2_MCSPI_MODULCTRL_STEST (1 << 3)
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#define OMAP2_MCSPI_CHCONF_PHA (1 << 0)
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#define OMAP2_MCSPI_CHCONF_POL (1 << 1)
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#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
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#define OMAP2_MCSPI_CHCONF_EPOL (1 << 6)
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#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
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#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
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#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
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#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
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#define OMAP2_MCSPI_CHCONF_DMAW (1 << 14)
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#define OMAP2_MCSPI_CHCONF_DMAR (1 << 15)
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#define OMAP2_MCSPI_CHCONF_DPE0 (1 << 16)
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#define OMAP2_MCSPI_CHCONF_DPE1 (1 << 17)
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#define OMAP2_MCSPI_CHCONF_IS (1 << 18)
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#define OMAP2_MCSPI_CHCONF_TURBO (1 << 19)
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#define OMAP2_MCSPI_CHCONF_FORCE (1 << 20)
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#define OMAP2_MCSPI_CHSTAT_RXS (1 << 0)
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#define OMAP2_MCSPI_CHSTAT_TXS (1 << 1)
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#define OMAP2_MCSPI_CHSTAT_EOT (1 << 2)
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#define OMAP2_MCSPI_CHCTRL_EN (1 << 0)
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/* We have 2 DMA channels per CS, one for RX and one for TX */
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struct omap2_mcspi_dma {
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int dma_tx_channel;
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int dma_rx_channel;
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int dma_tx_sync_dev;
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int dma_rx_sync_dev;
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struct completion dma_tx_completion;
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struct completion dma_rx_completion;
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};
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/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
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* cache operations; better heuristics consider wordsize and bitrate.
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*/
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#define DMA_MIN_BYTES 8
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struct omap2_mcspi {
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struct work_struct work;
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/* lock protects queue and registers */
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spinlock_t lock;
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struct list_head msg_queue;
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struct spi_master *master;
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struct clk *ick;
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struct clk *fck;
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/* Virtual base address of the controller */
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void __iomem *base;
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/* SPI1 has 4 channels, while SPI2 has 2 */
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struct omap2_mcspi_dma *dma_channels;
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};
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struct omap2_mcspi_cs {
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void __iomem *base;
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int word_len;
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};
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static struct workqueue_struct *omap2_mcspi_wq;
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#define MOD_REG_BIT(val, mask, set) do { \
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if (set) \
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val |= mask; \
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else \
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val &= ~mask; \
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} while (0)
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static inline void mcspi_write_reg(struct spi_master *master,
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int idx, u32 val)
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{
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struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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__raw_writel(val, mcspi->base + idx);
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}
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static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
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{
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struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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return __raw_readl(mcspi->base + idx);
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}
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static inline void mcspi_write_cs_reg(const struct spi_device *spi,
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int idx, u32 val)
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{
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struct omap2_mcspi_cs *cs = spi->controller_state;
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__raw_writel(val, cs->base + idx);
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}
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static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
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{
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struct omap2_mcspi_cs *cs = spi->controller_state;
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return __raw_readl(cs->base + idx);
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}
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static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
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int is_read, int enable)
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{
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u32 l, rw;
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l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
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if (is_read) /* 1 is read, 0 write */
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rw = OMAP2_MCSPI_CHCONF_DMAR;
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else
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rw = OMAP2_MCSPI_CHCONF_DMAW;
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MOD_REG_BIT(l, rw, enable);
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mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
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}
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static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
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{
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u32 l;
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l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
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mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
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}
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static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
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{
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u32 l;
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l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
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MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
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mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
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}
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static void omap2_mcspi_set_master_mode(struct spi_master *master)
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{
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u32 l;
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/* setup when switching from (reset default) slave mode
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* to single-channel master mode
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*/
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l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
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MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
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MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
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MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
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mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
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}
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static unsigned
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omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
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{
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struct omap2_mcspi *mcspi;
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struct omap2_mcspi_cs *cs = spi->controller_state;
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struct omap2_mcspi_dma *mcspi_dma;
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unsigned int count, c;
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unsigned long base, tx_reg, rx_reg;
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int word_len, data_type, element_count;
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u8 * rx;
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const u8 * tx;
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mcspi = spi_master_get_devdata(spi->master);
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mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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count = xfer->len;
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c = count;
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word_len = cs->word_len;
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base = (unsigned long) io_v2p(cs->base);
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tx_reg = base + OMAP2_MCSPI_TX0;
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rx_reg = base + OMAP2_MCSPI_RX0;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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if (word_len <= 8) {
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data_type = OMAP_DMA_DATA_TYPE_S8;
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element_count = count;
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} else if (word_len <= 16) {
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data_type = OMAP_DMA_DATA_TYPE_S16;
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element_count = count >> 1;
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} else /* word_len <= 32 */ {
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data_type = OMAP_DMA_DATA_TYPE_S32;
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element_count = count >> 2;
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}
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if (tx != NULL) {
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omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
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data_type, element_count, 1,
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OMAP_DMA_SYNC_ELEMENT,
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mcspi_dma->dma_tx_sync_dev, 0);
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omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
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OMAP_DMA_AMODE_CONSTANT,
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tx_reg, 0, 0);
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omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
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OMAP_DMA_AMODE_POST_INC,
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xfer->tx_dma, 0, 0);
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}
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if (rx != NULL) {
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omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
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data_type, element_count, 1,
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OMAP_DMA_SYNC_ELEMENT,
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mcspi_dma->dma_rx_sync_dev, 1);
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omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
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OMAP_DMA_AMODE_CONSTANT,
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rx_reg, 0, 0);
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omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
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OMAP_DMA_AMODE_POST_INC,
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xfer->rx_dma, 0, 0);
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}
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if (tx != NULL) {
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omap_start_dma(mcspi_dma->dma_tx_channel);
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omap2_mcspi_set_dma_req(spi, 0, 1);
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}
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if (rx != NULL) {
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omap_start_dma(mcspi_dma->dma_rx_channel);
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omap2_mcspi_set_dma_req(spi, 1, 1);
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}
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if (tx != NULL) {
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wait_for_completion(&mcspi_dma->dma_tx_completion);
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dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
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}
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if (rx != NULL) {
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wait_for_completion(&mcspi_dma->dma_rx_completion);
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dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
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}
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return count;
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}
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static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
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{
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unsigned long timeout;
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timeout = jiffies + msecs_to_jiffies(1000);
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while (!(__raw_readl(reg) & bit)) {
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if (time_after(jiffies, timeout))
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return -1;
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cpu_relax();
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}
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return 0;
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}
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static unsigned
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omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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{
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struct omap2_mcspi *mcspi;
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struct omap2_mcspi_cs *cs = spi->controller_state;
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unsigned int count, c;
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u32 l;
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void __iomem *base = cs->base;
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void __iomem *tx_reg;
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void __iomem *rx_reg;
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void __iomem *chstat_reg;
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int word_len;
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mcspi = spi_master_get_devdata(spi->master);
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count = xfer->len;
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c = count;
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word_len = cs->word_len;
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l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
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l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
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/* We store the pre-calculated register addresses on stack to speed
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* up the transfer loop. */
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tx_reg = base + OMAP2_MCSPI_TX0;
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rx_reg = base + OMAP2_MCSPI_RX0;
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chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
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if (word_len <= 8) {
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u8 *rx;
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const u8 *tx;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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do {
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if (tx != NULL) {
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if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_TXS) < 0) {
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dev_err(&spi->dev, "TXS timed out\n");
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goto out;
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}
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "write-%d %02x\n",
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word_len, *tx);
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#endif
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__raw_writel(*tx++, tx_reg);
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}
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if (rx != NULL) {
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if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_RXS) < 0) {
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dev_err(&spi->dev, "RXS timed out\n");
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goto out;
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}
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/* prevent last RX_ONLY read from triggering
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* more word i/o: switch to rx+tx
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*/
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if (c == 0 && tx == NULL)
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mcspi_write_cs_reg(spi,
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OMAP2_MCSPI_CHCONF0, l);
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*rx++ = __raw_readl(rx_reg);
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "read-%d %02x\n",
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word_len, *(rx - 1));
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#endif
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}
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c -= 1;
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} while (c);
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} else if (word_len <= 16) {
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u16 *rx;
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const u16 *tx;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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do {
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if (tx != NULL) {
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if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_TXS) < 0) {
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dev_err(&spi->dev, "TXS timed out\n");
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goto out;
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}
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "write-%d %04x\n",
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word_len, *tx);
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#endif
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__raw_writel(*tx++, tx_reg);
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}
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if (rx != NULL) {
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if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_RXS) < 0) {
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dev_err(&spi->dev, "RXS timed out\n");
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goto out;
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}
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/* prevent last RX_ONLY read from triggering
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* more word i/o: switch to rx+tx
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*/
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if (c == 0 && tx == NULL)
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mcspi_write_cs_reg(spi,
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OMAP2_MCSPI_CHCONF0, l);
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*rx++ = __raw_readl(rx_reg);
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "read-%d %04x\n",
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word_len, *(rx - 1));
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#endif
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}
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c -= 2;
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} while (c);
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} else if (word_len <= 32) {
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u32 *rx;
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const u32 *tx;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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do {
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if (tx != NULL) {
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if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_TXS) < 0) {
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dev_err(&spi->dev, "TXS timed out\n");
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goto out;
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}
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "write-%d %04x\n",
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word_len, *tx);
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#endif
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__raw_writel(*tx++, tx_reg);
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}
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if (rx != NULL) {
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if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_RXS) < 0) {
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dev_err(&spi->dev, "RXS timed out\n");
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goto out;
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}
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/* prevent last RX_ONLY read from triggering
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* more word i/o: switch to rx+tx
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*/
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if (c == 0 && tx == NULL)
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mcspi_write_cs_reg(spi,
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OMAP2_MCSPI_CHCONF0, l);
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*rx++ = __raw_readl(rx_reg);
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#ifdef VERBOSE
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dev_dbg(&spi->dev, "read-%d %04x\n",
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word_len, *(rx - 1));
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#endif
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}
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c -= 4;
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} while (c);
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}
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/* for TX_ONLY mode, be sure all words have shifted out */
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if (xfer->rx_buf == NULL) {
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if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_TXS) < 0) {
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dev_err(&spi->dev, "TXS timed out\n");
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} else if (mcspi_wait_for_reg_bit(chstat_reg,
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OMAP2_MCSPI_CHSTAT_EOT) < 0)
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dev_err(&spi->dev, "EOT timed out\n");
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}
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out:
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return count - c;
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}
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/* called only when no transfer is active to this device */
|
|
static int omap2_mcspi_setup_transfer(struct spi_device *spi,
|
|
struct spi_transfer *t)
|
|
{
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
struct omap2_mcspi *mcspi;
|
|
u32 l = 0, div = 0;
|
|
u8 word_len = spi->bits_per_word;
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
if (t != NULL && t->bits_per_word)
|
|
word_len = t->bits_per_word;
|
|
|
|
cs->word_len = word_len;
|
|
|
|
if (spi->max_speed_hz) {
|
|
while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
|
|
> spi->max_speed_hz)
|
|
div++;
|
|
} else
|
|
div = 15;
|
|
|
|
l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
|
|
|
|
/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
|
|
* REVISIT: this controller could support SPI_3WIRE mode.
|
|
*/
|
|
l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
|
|
l |= OMAP2_MCSPI_CHCONF_DPE0;
|
|
|
|
/* wordlength */
|
|
l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
|
|
l |= (word_len - 1) << 7;
|
|
|
|
/* set chipselect polarity; manage with FORCE */
|
|
if (!(spi->mode & SPI_CS_HIGH))
|
|
l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
|
|
else
|
|
l &= ~OMAP2_MCSPI_CHCONF_EPOL;
|
|
|
|
/* set clock divisor */
|
|
l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
|
|
l |= div << 2;
|
|
|
|
/* set SPI mode 0..3 */
|
|
if (spi->mode & SPI_CPOL)
|
|
l |= OMAP2_MCSPI_CHCONF_POL;
|
|
else
|
|
l &= ~OMAP2_MCSPI_CHCONF_POL;
|
|
if (spi->mode & SPI_CPHA)
|
|
l |= OMAP2_MCSPI_CHCONF_PHA;
|
|
else
|
|
l &= ~OMAP2_MCSPI_CHCONF_PHA;
|
|
|
|
mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
|
|
|
|
dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
|
|
OMAP2_MCSPI_MAX_FREQ / (1 << div),
|
|
(spi->mode & SPI_CPHA) ? "trailing" : "leading",
|
|
(spi->mode & SPI_CPOL) ? "inverted" : "normal");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
|
|
{
|
|
struct spi_device *spi = data;
|
|
struct omap2_mcspi *mcspi;
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
|
|
|
|
complete(&mcspi_dma->dma_rx_completion);
|
|
|
|
/* We must disable the DMA RX request */
|
|
omap2_mcspi_set_dma_req(spi, 1, 0);
|
|
}
|
|
|
|
static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
|
|
{
|
|
struct spi_device *spi = data;
|
|
struct omap2_mcspi *mcspi;
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
|
|
|
|
complete(&mcspi_dma->dma_tx_completion);
|
|
|
|
/* We must disable the DMA TX request */
|
|
omap2_mcspi_set_dma_req(spi, 0, 0);
|
|
}
|
|
|
|
static int omap2_mcspi_request_dma(struct spi_device *spi)
|
|
{
|
|
struct spi_master *master = spi->master;
|
|
struct omap2_mcspi *mcspi;
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
mcspi_dma = mcspi->dma_channels + spi->chip_select;
|
|
|
|
if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
|
|
omap2_mcspi_dma_rx_callback, spi,
|
|
&mcspi_dma->dma_rx_channel)) {
|
|
dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
|
|
return -EAGAIN;
|
|
}
|
|
|
|
if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
|
|
omap2_mcspi_dma_tx_callback, spi,
|
|
&mcspi_dma->dma_tx_channel)) {
|
|
omap_free_dma(mcspi_dma->dma_rx_channel);
|
|
mcspi_dma->dma_rx_channel = -1;
|
|
dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
|
|
return -EAGAIN;
|
|
}
|
|
|
|
init_completion(&mcspi_dma->dma_rx_completion);
|
|
init_completion(&mcspi_dma->dma_tx_completion);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* the spi->mode bits understood by this driver: */
|
|
#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
|
|
|
|
static int omap2_mcspi_setup(struct spi_device *spi)
|
|
{
|
|
int ret;
|
|
struct omap2_mcspi *mcspi;
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
if (spi->mode & ~MODEBITS) {
|
|
dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
|
|
spi->mode & ~MODEBITS);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (spi->bits_per_word == 0)
|
|
spi->bits_per_word = 8;
|
|
else if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
|
|
dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
|
|
spi->bits_per_word);
|
|
return -EINVAL;
|
|
}
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
mcspi_dma = &mcspi->dma_channels[spi->chip_select];
|
|
|
|
if (!cs) {
|
|
cs = kzalloc(sizeof *cs, GFP_KERNEL);
|
|
if (!cs)
|
|
return -ENOMEM;
|
|
cs->base = mcspi->base + spi->chip_select * 0x14;
|
|
spi->controller_state = cs;
|
|
}
|
|
|
|
if (mcspi_dma->dma_rx_channel == -1
|
|
|| mcspi_dma->dma_tx_channel == -1) {
|
|
ret = omap2_mcspi_request_dma(spi);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
clk_enable(mcspi->ick);
|
|
clk_enable(mcspi->fck);
|
|
ret = omap2_mcspi_setup_transfer(spi, NULL);
|
|
clk_disable(mcspi->fck);
|
|
clk_disable(mcspi->ick);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void omap2_mcspi_cleanup(struct spi_device *spi)
|
|
{
|
|
struct omap2_mcspi *mcspi;
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
mcspi_dma = &mcspi->dma_channels[spi->chip_select];
|
|
|
|
kfree(spi->controller_state);
|
|
|
|
if (mcspi_dma->dma_rx_channel != -1) {
|
|
omap_free_dma(mcspi_dma->dma_rx_channel);
|
|
mcspi_dma->dma_rx_channel = -1;
|
|
}
|
|
if (mcspi_dma->dma_tx_channel != -1) {
|
|
omap_free_dma(mcspi_dma->dma_tx_channel);
|
|
mcspi_dma->dma_tx_channel = -1;
|
|
}
|
|
}
|
|
|
|
static void omap2_mcspi_work(struct work_struct *work)
|
|
{
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
mcspi = container_of(work, struct omap2_mcspi, work);
|
|
spin_lock_irq(&mcspi->lock);
|
|
|
|
clk_enable(mcspi->ick);
|
|
clk_enable(mcspi->fck);
|
|
|
|
/* We only enable one channel at a time -- the one whose message is
|
|
* at the head of the queue -- although this controller would gladly
|
|
* arbitrate among multiple channels. This corresponds to "single
|
|
* channel" master mode. As a side effect, we need to manage the
|
|
* chipselect with the FORCE bit ... CS != channel enable.
|
|
*/
|
|
while (!list_empty(&mcspi->msg_queue)) {
|
|
struct spi_message *m;
|
|
struct spi_device *spi;
|
|
struct spi_transfer *t = NULL;
|
|
int cs_active = 0;
|
|
struct omap2_mcspi_cs *cs;
|
|
int par_override = 0;
|
|
int status = 0;
|
|
u32 chconf;
|
|
|
|
m = container_of(mcspi->msg_queue.next, struct spi_message,
|
|
queue);
|
|
|
|
list_del_init(&m->queue);
|
|
spin_unlock_irq(&mcspi->lock);
|
|
|
|
spi = m->spi;
|
|
cs = spi->controller_state;
|
|
|
|
omap2_mcspi_set_enable(spi, 1);
|
|
list_for_each_entry(t, &m->transfers, transfer_list) {
|
|
if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
|
|
status = -EINVAL;
|
|
break;
|
|
}
|
|
if (par_override || t->speed_hz || t->bits_per_word) {
|
|
par_override = 1;
|
|
status = omap2_mcspi_setup_transfer(spi, t);
|
|
if (status < 0)
|
|
break;
|
|
if (!t->speed_hz && !t->bits_per_word)
|
|
par_override = 0;
|
|
}
|
|
|
|
if (!cs_active) {
|
|
omap2_mcspi_force_cs(spi, 1);
|
|
cs_active = 1;
|
|
}
|
|
|
|
chconf = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
|
|
chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
|
|
if (t->tx_buf == NULL)
|
|
chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
|
|
else if (t->rx_buf == NULL)
|
|
chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
|
|
mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, chconf);
|
|
|
|
if (t->len) {
|
|
unsigned count;
|
|
|
|
/* RX_ONLY mode needs dummy data in TX reg */
|
|
if (t->tx_buf == NULL)
|
|
__raw_writel(0, cs->base
|
|
+ OMAP2_MCSPI_TX0);
|
|
|
|
if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
|
|
count = omap2_mcspi_txrx_dma(spi, t);
|
|
else
|
|
count = omap2_mcspi_txrx_pio(spi, t);
|
|
m->actual_length += count;
|
|
|
|
if (count != t->len) {
|
|
status = -EIO;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (t->delay_usecs)
|
|
udelay(t->delay_usecs);
|
|
|
|
/* ignore the "leave it on after last xfer" hint */
|
|
if (t->cs_change) {
|
|
omap2_mcspi_force_cs(spi, 0);
|
|
cs_active = 0;
|
|
}
|
|
}
|
|
|
|
/* Restore defaults if they were overriden */
|
|
if (par_override) {
|
|
par_override = 0;
|
|
status = omap2_mcspi_setup_transfer(spi, NULL);
|
|
}
|
|
|
|
if (cs_active)
|
|
omap2_mcspi_force_cs(spi, 0);
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
|
|
|
m->status = status;
|
|
m->complete(m->context);
|
|
|
|
spin_lock_irq(&mcspi->lock);
|
|
}
|
|
|
|
clk_disable(mcspi->fck);
|
|
clk_disable(mcspi->ick);
|
|
|
|
spin_unlock_irq(&mcspi->lock);
|
|
}
|
|
|
|
static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
|
|
{
|
|
struct omap2_mcspi *mcspi;
|
|
unsigned long flags;
|
|
struct spi_transfer *t;
|
|
|
|
m->actual_length = 0;
|
|
m->status = 0;
|
|
|
|
/* reject invalid messages and transfers */
|
|
if (list_empty(&m->transfers) || !m->complete)
|
|
return -EINVAL;
|
|
list_for_each_entry(t, &m->transfers, transfer_list) {
|
|
const void *tx_buf = t->tx_buf;
|
|
void *rx_buf = t->rx_buf;
|
|
unsigned len = t->len;
|
|
|
|
if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
|
|
|| (len && !(rx_buf || tx_buf))
|
|
|| (t->bits_per_word &&
|
|
( t->bits_per_word < 4
|
|
|| t->bits_per_word > 32))) {
|
|
dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
|
|
t->speed_hz,
|
|
len,
|
|
tx_buf ? "tx" : "",
|
|
rx_buf ? "rx" : "",
|
|
t->bits_per_word);
|
|
return -EINVAL;
|
|
}
|
|
if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
|
|
dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
|
|
t->speed_hz,
|
|
OMAP2_MCSPI_MAX_FREQ/(1<<16));
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (m->is_dma_mapped || len < DMA_MIN_BYTES)
|
|
continue;
|
|
|
|
/* Do DMA mapping "early" for better error reporting and
|
|
* dcache use. Note that if dma_unmap_single() ever starts
|
|
* to do real work on ARM, we'd need to clean up mappings
|
|
* for previous transfers on *ALL* exits of this loop...
|
|
*/
|
|
if (tx_buf != NULL) {
|
|
t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
|
|
len, DMA_TO_DEVICE);
|
|
if (dma_mapping_error(t->tx_dma)) {
|
|
dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
|
|
'T', len);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
if (rx_buf != NULL) {
|
|
t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
|
|
DMA_FROM_DEVICE);
|
|
if (dma_mapping_error(t->rx_dma)) {
|
|
dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
|
|
'R', len);
|
|
if (tx_buf != NULL)
|
|
dma_unmap_single(NULL, t->tx_dma,
|
|
len, DMA_TO_DEVICE);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
}
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
spin_lock_irqsave(&mcspi->lock, flags);
|
|
list_add_tail(&m->queue, &mcspi->msg_queue);
|
|
queue_work(omap2_mcspi_wq, &mcspi->work);
|
|
spin_unlock_irqrestore(&mcspi->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
|
|
{
|
|
struct spi_master *master = mcspi->master;
|
|
u32 tmp;
|
|
|
|
clk_enable(mcspi->ick);
|
|
clk_enable(mcspi->fck);
|
|
|
|
mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
|
|
OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
|
|
do {
|
|
tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
|
|
} while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
|
|
|
|
mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
|
|
/* (3 << 8) | (2 << 3) | */
|
|
OMAP2_MCSPI_SYSCONFIG_AUTOIDLE);
|
|
|
|
omap2_mcspi_set_master_mode(master);
|
|
|
|
clk_disable(mcspi->fck);
|
|
clk_disable(mcspi->ick);
|
|
return 0;
|
|
}
|
|
|
|
static u8 __initdata spi1_rxdma_id [] = {
|
|
OMAP24XX_DMA_SPI1_RX0,
|
|
OMAP24XX_DMA_SPI1_RX1,
|
|
OMAP24XX_DMA_SPI1_RX2,
|
|
OMAP24XX_DMA_SPI1_RX3,
|
|
};
|
|
|
|
static u8 __initdata spi1_txdma_id [] = {
|
|
OMAP24XX_DMA_SPI1_TX0,
|
|
OMAP24XX_DMA_SPI1_TX1,
|
|
OMAP24XX_DMA_SPI1_TX2,
|
|
OMAP24XX_DMA_SPI1_TX3,
|
|
};
|
|
|
|
static u8 __initdata spi2_rxdma_id[] = {
|
|
OMAP24XX_DMA_SPI2_RX0,
|
|
OMAP24XX_DMA_SPI2_RX1,
|
|
};
|
|
|
|
static u8 __initdata spi2_txdma_id[] = {
|
|
OMAP24XX_DMA_SPI2_TX0,
|
|
OMAP24XX_DMA_SPI2_TX1,
|
|
};
|
|
|
|
static int __init omap2_mcspi_probe(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master;
|
|
struct omap2_mcspi *mcspi;
|
|
struct resource *r;
|
|
int status = 0, i;
|
|
const u8 *rxdma_id, *txdma_id;
|
|
unsigned num_chipselect;
|
|
|
|
switch (pdev->id) {
|
|
case 1:
|
|
rxdma_id = spi1_rxdma_id;
|
|
txdma_id = spi1_txdma_id;
|
|
num_chipselect = 4;
|
|
break;
|
|
case 2:
|
|
rxdma_id = spi2_rxdma_id;
|
|
txdma_id = spi2_txdma_id;
|
|
num_chipselect = 2;
|
|
break;
|
|
/* REVISIT omap2430 has a third McSPI ... */
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
|
|
if (master == NULL) {
|
|
dev_dbg(&pdev->dev, "master allocation failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (pdev->id != -1)
|
|
master->bus_num = pdev->id;
|
|
|
|
master->setup = omap2_mcspi_setup;
|
|
master->transfer = omap2_mcspi_transfer;
|
|
master->cleanup = omap2_mcspi_cleanup;
|
|
master->num_chipselect = num_chipselect;
|
|
|
|
dev_set_drvdata(&pdev->dev, master);
|
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
mcspi->master = master;
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (r == NULL) {
|
|
status = -ENODEV;
|
|
goto err1;
|
|
}
|
|
if (!request_mem_region(r->start, (r->end - r->start) + 1,
|
|
pdev->dev.bus_id)) {
|
|
status = -EBUSY;
|
|
goto err1;
|
|
}
|
|
|
|
mcspi->base = (void __iomem *) io_p2v(r->start);
|
|
|
|
INIT_WORK(&mcspi->work, omap2_mcspi_work);
|
|
|
|
spin_lock_init(&mcspi->lock);
|
|
INIT_LIST_HEAD(&mcspi->msg_queue);
|
|
|
|
mcspi->ick = clk_get(&pdev->dev, "mcspi_ick");
|
|
if (IS_ERR(mcspi->ick)) {
|
|
dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
|
|
status = PTR_ERR(mcspi->ick);
|
|
goto err1a;
|
|
}
|
|
mcspi->fck = clk_get(&pdev->dev, "mcspi_fck");
|
|
if (IS_ERR(mcspi->fck)) {
|
|
dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
|
|
status = PTR_ERR(mcspi->fck);
|
|
goto err2;
|
|
}
|
|
|
|
mcspi->dma_channels = kcalloc(master->num_chipselect,
|
|
sizeof(struct omap2_mcspi_dma),
|
|
GFP_KERNEL);
|
|
|
|
if (mcspi->dma_channels == NULL)
|
|
goto err3;
|
|
|
|
for (i = 0; i < num_chipselect; i++) {
|
|
mcspi->dma_channels[i].dma_rx_channel = -1;
|
|
mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
|
|
mcspi->dma_channels[i].dma_tx_channel = -1;
|
|
mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
|
|
}
|
|
|
|
if (omap2_mcspi_reset(mcspi) < 0)
|
|
goto err4;
|
|
|
|
status = spi_register_master(master);
|
|
if (status < 0)
|
|
goto err4;
|
|
|
|
return status;
|
|
|
|
err4:
|
|
kfree(mcspi->dma_channels);
|
|
err3:
|
|
clk_put(mcspi->fck);
|
|
err2:
|
|
clk_put(mcspi->ick);
|
|
err1a:
|
|
release_mem_region(r->start, (r->end - r->start) + 1);
|
|
err1:
|
|
spi_master_put(master);
|
|
return status;
|
|
}
|
|
|
|
static int __exit omap2_mcspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master;
|
|
struct omap2_mcspi *mcspi;
|
|
struct omap2_mcspi_dma *dma_channels;
|
|
struct resource *r;
|
|
|
|
master = dev_get_drvdata(&pdev->dev);
|
|
mcspi = spi_master_get_devdata(master);
|
|
dma_channels = mcspi->dma_channels;
|
|
|
|
clk_put(mcspi->fck);
|
|
clk_put(mcspi->ick);
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
release_mem_region(r->start, (r->end - r->start) + 1);
|
|
|
|
spi_unregister_master(master);
|
|
kfree(dma_channels);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver omap2_mcspi_driver = {
|
|
.driver = {
|
|
.name = "omap2_mcspi",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.remove = __exit_p(omap2_mcspi_remove),
|
|
};
|
|
|
|
|
|
static int __init omap2_mcspi_init(void)
|
|
{
|
|
omap2_mcspi_wq = create_singlethread_workqueue(
|
|
omap2_mcspi_driver.driver.name);
|
|
if (omap2_mcspi_wq == NULL)
|
|
return -1;
|
|
return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
|
|
}
|
|
subsys_initcall(omap2_mcspi_init);
|
|
|
|
static void __exit omap2_mcspi_exit(void)
|
|
{
|
|
platform_driver_unregister(&omap2_mcspi_driver);
|
|
|
|
destroy_workqueue(omap2_mcspi_wq);
|
|
}
|
|
module_exit(omap2_mcspi_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|