Heiko Stuebner 18d5408932 drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores ... With the T-HEAD C9XX cores being designed before or during the ratification to the SSCOFPMF extension, it implements functionality very similar but not equal to it. It implements overflow handling and also some privilege-mode filtering. While SSCOFPMF supports this for all modes, the C9XX only implements the filtering for M-mode and S-mode but not user-mode. So add some adaptions to allow the C9XX to still handle its PMU through the regular SBI PMU interface instead of defining new interfaces or drivers. To work properly, this requires a matching change in SBI, though the actual interface between kernel and SBI does not change. The main differences are a the overflow CSR and irq number. As the reading of the overflow-csr is in the hot-path during irq handling, use an errata and alternatives to not introduce new conditionals there. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/all/20221011231841.2951264-2-heiko@sntech.de/ Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2024-03-04 09:58:22 +08:00
..
sifive	RISC-V: fix taking the text_mutex twice during sifive errata patching	2023-05-17 11:53:41 +02:00
thead	drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores	2024-03-04 09:58:22 +08:00
Makefile	riscv: add memory-type errata for T-Head	2022-05-11 21:36:33 -07:00