Catalin Marinas a41dc0e841 arm64: Implement cache_line_size() based on CTR_EL0.CWG ... The hardware provides the maximum cache line size in the system via the CTR_EL0.CWG bits. This patch implements the cache_line_size() function to read such information, together with a sanity check if the statically defined L1_CACHE_BYTES is smaller than the hardware value. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Will Deacon <will.deacon@arm.com>		2014-05-09 15:47:45 +01:00
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boot	arm64: Mark the Applied Micro X-Gene SATA controller as DMA coherent	2014-05-03 22:20:35 +01:00
configs	arm64: defconfig: Expand default enabled features	2014-02-07 17:17:28 +00:00
include	arm64: Implement cache_line_size() based on CTR_EL0.CWG	2014-05-09 15:47:45 +01:00
kernel	arm64: Implement cache_line_size() based on CTR_EL0.CWG	2014-05-09 15:47:45 +01:00
kvm	Merge tag 'kvm-3.15-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm	2014-04-02 14:50:10 -07:00
lib	arm64: atomics: fix use of acquire + release for full barrier semantics	2014-02-07 16:45:43 +00:00
mm	arm64: Use bus notifiers to set per-device coherent DMA ops	2014-05-03 22:20:34 +01:00
xen	xen/arm,arm64: enable SWIOTLB_XEN	2013-10-10 13:40:44 +00:00
Kconfig	arm64: Implement cache_line_size() based on CTR_EL0.CWG	2014-05-09 15:47:45 +01:00
Kconfig.debug	arm64: Add missing Kconfig for CONFIG_STRICT_DEVMEM	2014-04-07 17:33:13 +01:00
Makefile	arm64: big-endian: add big-endian support to top-level arch Makefile	2013-10-25 15:59:31 +01:00