582 lines
14 KiB
C
582 lines
14 KiB
C
/*
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*
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* Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/mutex.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <linux/time.h>
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#include <sound/core.h>
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#include <sound/initval.h>
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#include "hda_codec.h"
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#include "hda_controller.h"
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/* Defines for Nvidia Tegra HDA support */
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#define HDA_BAR0 0x8000
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#define HDA_CFG_CMD 0x1004
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#define HDA_CFG_BAR0 0x1010
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#define HDA_ENABLE_IO_SPACE (1 << 0)
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#define HDA_ENABLE_MEM_SPACE (1 << 1)
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#define HDA_ENABLE_BUS_MASTER (1 << 2)
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#define HDA_ENABLE_SERR (1 << 8)
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#define HDA_DISABLE_INTR (1 << 10)
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#define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
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#define HDA_BAR0_FINAL_PROGRAM (1 << 14)
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/* IPFS */
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#define HDA_IPFS_CONFIG 0x180
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#define HDA_IPFS_EN_FPCI 0x1
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#define HDA_IPFS_FPCI_BAR0 0x80
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#define HDA_FPCI_BAR0_START 0x40
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#define HDA_IPFS_INTR_MASK 0x188
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#define HDA_IPFS_EN_INTR (1 << 16)
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/* max number of SDs */
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#define NUM_CAPTURE_SD 1
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#define NUM_PLAYBACK_SD 1
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struct hda_tegra {
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struct azx chip;
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struct device *dev;
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struct clk *hda_clk;
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struct clk *hda2codec_2x_clk;
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struct clk *hda2hdmi_clk;
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void __iomem *regs;
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struct work_struct probe_work;
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};
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#ifdef CONFIG_PM
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static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
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module_param(power_save, bint, 0644);
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MODULE_PARM_DESC(power_save,
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"Automatic power-saving timeout (in seconds, 0 = disable).");
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#else
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#define power_save 0
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#endif
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/*
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* DMA page allocation ops.
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*/
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static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size,
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struct snd_dma_buffer *buf)
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{
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return snd_dma_alloc_pages(type, bus->dev, size, buf);
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}
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static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
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{
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snd_dma_free_pages(buf);
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}
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static int substream_alloc_pages(struct azx *chip,
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struct snd_pcm_substream *substream,
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size_t size)
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{
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return snd_pcm_lib_malloc_pages(substream, size);
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}
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static int substream_free_pages(struct azx *chip,
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struct snd_pcm_substream *substream)
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{
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return snd_pcm_lib_free_pages(substream);
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}
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/*
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* Register access ops. Tegra HDA register access is DWORD only.
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*/
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static void hda_tegra_writel(u32 value, u32 __iomem *addr)
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{
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writel(value, addr);
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}
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static u32 hda_tegra_readl(u32 __iomem *addr)
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{
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return readl(addr);
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}
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static void hda_tegra_writew(u16 value, u16 __iomem *addr)
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{
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unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
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void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
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u32 v;
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v = readl(dword_addr);
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v &= ~(0xffff << shift);
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v |= value << shift;
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writel(v, dword_addr);
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}
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static u16 hda_tegra_readw(u16 __iomem *addr)
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{
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unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
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void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
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u32 v;
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v = readl(dword_addr);
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return (v >> shift) & 0xffff;
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}
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static void hda_tegra_writeb(u8 value, u8 __iomem *addr)
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{
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unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
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void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
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u32 v;
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v = readl(dword_addr);
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v &= ~(0xff << shift);
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v |= value << shift;
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writel(v, dword_addr);
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}
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static u8 hda_tegra_readb(u8 __iomem *addr)
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{
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unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
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void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3);
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u32 v;
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v = readl(dword_addr);
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return (v >> shift) & 0xff;
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}
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static const struct hdac_io_ops hda_tegra_io_ops = {
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.reg_writel = hda_tegra_writel,
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.reg_readl = hda_tegra_readl,
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.reg_writew = hda_tegra_writew,
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.reg_readw = hda_tegra_readw,
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.reg_writeb = hda_tegra_writeb,
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.reg_readb = hda_tegra_readb,
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.dma_alloc_pages = dma_alloc_pages,
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.dma_free_pages = dma_free_pages,
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};
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static const struct hda_controller_ops hda_tegra_ops = {
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.substream_alloc_pages = substream_alloc_pages,
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.substream_free_pages = substream_free_pages,
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};
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static void hda_tegra_init(struct hda_tegra *hda)
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{
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u32 v;
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/* Enable PCI access */
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v = readl(hda->regs + HDA_IPFS_CONFIG);
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v |= HDA_IPFS_EN_FPCI;
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writel(v, hda->regs + HDA_IPFS_CONFIG);
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/* Enable MEM/IO space and bus master */
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v = readl(hda->regs + HDA_CFG_CMD);
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v &= ~HDA_DISABLE_INTR;
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v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
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HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
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writel(v, hda->regs + HDA_CFG_CMD);
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writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
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writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
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writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
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v = readl(hda->regs + HDA_IPFS_INTR_MASK);
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v |= HDA_IPFS_EN_INTR;
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writel(v, hda->regs + HDA_IPFS_INTR_MASK);
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}
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static int hda_tegra_enable_clocks(struct hda_tegra *data)
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{
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int rc;
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rc = clk_prepare_enable(data->hda_clk);
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if (rc)
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return rc;
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rc = clk_prepare_enable(data->hda2codec_2x_clk);
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if (rc)
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goto disable_hda;
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rc = clk_prepare_enable(data->hda2hdmi_clk);
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if (rc)
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goto disable_codec_2x;
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return 0;
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disable_codec_2x:
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clk_disable_unprepare(data->hda2codec_2x_clk);
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disable_hda:
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clk_disable_unprepare(data->hda_clk);
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return rc;
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}
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#ifdef CONFIG_PM_SLEEP
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static void hda_tegra_disable_clocks(struct hda_tegra *data)
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{
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clk_disable_unprepare(data->hda2hdmi_clk);
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clk_disable_unprepare(data->hda2codec_2x_clk);
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clk_disable_unprepare(data->hda_clk);
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}
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/*
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* power management
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*/
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static int hda_tegra_suspend(struct device *dev)
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{
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struct snd_card *card = dev_get_drvdata(dev);
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struct azx *chip = card->private_data;
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struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
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snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
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azx_stop_chip(chip);
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azx_enter_link_reset(chip);
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hda_tegra_disable_clocks(hda);
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return 0;
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}
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static int hda_tegra_resume(struct device *dev)
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{
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struct snd_card *card = dev_get_drvdata(dev);
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struct azx *chip = card->private_data;
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struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
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hda_tegra_enable_clocks(hda);
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hda_tegra_init(hda);
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azx_init_chip(chip, 1);
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snd_power_change_state(card, SNDRV_CTL_POWER_D0);
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return 0;
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}
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#endif /* CONFIG_PM_SLEEP */
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static const struct dev_pm_ops hda_tegra_pm = {
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SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
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};
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static int hda_tegra_dev_disconnect(struct snd_device *device)
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{
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struct azx *chip = device->device_data;
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chip->bus.shutdown = 1;
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return 0;
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}
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/*
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* destructor
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*/
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static int hda_tegra_dev_free(struct snd_device *device)
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{
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struct azx *chip = device->device_data;
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struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
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cancel_work_sync(&hda->probe_work);
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if (azx_bus(chip)->chip_init) {
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azx_stop_all_streams(chip);
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azx_stop_chip(chip);
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}
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azx_free_stream_pages(chip);
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azx_free_streams(chip);
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snd_hdac_bus_exit(azx_bus(chip));
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return 0;
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}
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static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
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{
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struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
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struct hdac_bus *bus = azx_bus(chip);
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struct device *dev = hda->dev;
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struct resource *res;
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int err;
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hda->hda_clk = devm_clk_get(dev, "hda");
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if (IS_ERR(hda->hda_clk)) {
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dev_err(dev, "failed to get hda clock\n");
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return PTR_ERR(hda->hda_clk);
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}
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hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
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if (IS_ERR(hda->hda2codec_2x_clk)) {
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dev_err(dev, "failed to get hda2codec_2x clock\n");
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return PTR_ERR(hda->hda2codec_2x_clk);
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}
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hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
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if (IS_ERR(hda->hda2hdmi_clk)) {
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dev_err(dev, "failed to get hda2hdmi clock\n");
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return PTR_ERR(hda->hda2hdmi_clk);
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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hda->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(hda->regs))
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return PTR_ERR(hda->regs);
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bus->remap_addr = hda->regs + HDA_BAR0;
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bus->addr = res->start + HDA_BAR0;
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err = hda_tegra_enable_clocks(hda);
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if (err) {
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dev_err(dev, "failed to get enable clocks\n");
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return err;
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}
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hda_tegra_init(hda);
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return 0;
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}
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static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
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{
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struct hdac_bus *bus = azx_bus(chip);
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struct snd_card *card = chip->card;
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int err;
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unsigned short gcap;
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int irq_id = platform_get_irq(pdev, 0);
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err = hda_tegra_init_chip(chip, pdev);
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if (err)
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return err;
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err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
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IRQF_SHARED, KBUILD_MODNAME, chip);
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if (err) {
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dev_err(chip->card->dev,
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"unable to request IRQ %d, disabling device\n",
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irq_id);
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return err;
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}
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bus->irq = irq_id;
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synchronize_irq(bus->irq);
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gcap = azx_readw(chip, GCAP);
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dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
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/* read number of streams from GCAP register instead of using
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* hardcoded value
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*/
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chip->capture_streams = (gcap >> 8) & 0x0f;
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chip->playback_streams = (gcap >> 12) & 0x0f;
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if (!chip->playback_streams && !chip->capture_streams) {
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/* gcap didn't give any info, switching to old method */
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chip->playback_streams = NUM_PLAYBACK_SD;
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chip->capture_streams = NUM_CAPTURE_SD;
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}
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chip->capture_index_offset = 0;
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chip->playback_index_offset = chip->capture_streams;
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chip->num_streams = chip->playback_streams + chip->capture_streams;
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/* initialize streams */
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err = azx_init_streams(chip);
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if (err < 0) {
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dev_err(card->dev, "failed to initialize streams: %d\n", err);
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return err;
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}
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err = azx_alloc_stream_pages(chip);
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if (err < 0) {
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dev_err(card->dev, "failed to allocate stream pages: %d\n",
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err);
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return err;
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}
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/* initialize chip */
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azx_init_chip(chip, 1);
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/* codec detection */
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if (!bus->codec_mask) {
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dev_err(card->dev, "no codecs found!\n");
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return -ENODEV;
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}
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strcpy(card->driver, "tegra-hda");
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strcpy(card->shortname, "tegra-hda");
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snprintf(card->longname, sizeof(card->longname),
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"%s at 0x%lx irq %i",
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card->shortname, bus->addr, bus->irq);
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return 0;
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}
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/*
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* constructor
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*/
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static void hda_tegra_probe_work(struct work_struct *work);
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static int hda_tegra_create(struct snd_card *card,
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unsigned int driver_caps,
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struct hda_tegra *hda)
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{
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static struct snd_device_ops ops = {
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.dev_disconnect = hda_tegra_dev_disconnect,
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.dev_free = hda_tegra_dev_free,
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};
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struct azx *chip;
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int err;
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chip = &hda->chip;
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mutex_init(&chip->open_mutex);
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chip->card = card;
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chip->ops = &hda_tegra_ops;
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chip->driver_caps = driver_caps;
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chip->driver_type = driver_caps & 0xff;
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chip->dev_index = 0;
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INIT_LIST_HEAD(&chip->pcm_list);
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chip->codec_probe_mask = -1;
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chip->single_cmd = false;
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chip->snoop = true;
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INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
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err = azx_bus_init(chip, NULL, &hda_tegra_io_ops);
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if (err < 0)
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return err;
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chip->bus.needs_damn_long_delay = 1;
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err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
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if (err < 0) {
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dev_err(card->dev, "Error creating device\n");
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return err;
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}
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|
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return 0;
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}
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|
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static const struct of_device_id hda_tegra_match[] = {
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{ .compatible = "nvidia,tegra30-hda" },
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{},
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};
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MODULE_DEVICE_TABLE(of, hda_tegra_match);
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|
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static int hda_tegra_probe(struct platform_device *pdev)
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{
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const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR;
|
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struct snd_card *card;
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struct azx *chip;
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struct hda_tegra *hda;
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int err;
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|
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hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
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if (!hda)
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return -ENOMEM;
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hda->dev = &pdev->dev;
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chip = &hda->chip;
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|
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err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
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THIS_MODULE, 0, &card);
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if (err < 0) {
|
|
dev_err(&pdev->dev, "Error creating card!\n");
|
|
return err;
|
|
}
|
|
|
|
err = hda_tegra_create(card, driver_flags, hda);
|
|
if (err < 0)
|
|
goto out_free;
|
|
card->private_data = chip;
|
|
|
|
dev_set_drvdata(&pdev->dev, card);
|
|
schedule_work(&hda->probe_work);
|
|
|
|
return 0;
|
|
|
|
out_free:
|
|
snd_card_free(card);
|
|
return err;
|
|
}
|
|
|
|
static void hda_tegra_probe_work(struct work_struct *work)
|
|
{
|
|
struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
|
|
struct azx *chip = &hda->chip;
|
|
struct platform_device *pdev = to_platform_device(hda->dev);
|
|
int err;
|
|
|
|
err = hda_tegra_first_init(chip, pdev);
|
|
if (err < 0)
|
|
goto out_free;
|
|
|
|
/* create codec instances */
|
|
err = azx_probe_codecs(chip, 0);
|
|
if (err < 0)
|
|
goto out_free;
|
|
|
|
err = azx_codec_configure(chip);
|
|
if (err < 0)
|
|
goto out_free;
|
|
|
|
err = snd_card_register(chip->card);
|
|
if (err < 0)
|
|
goto out_free;
|
|
|
|
chip->running = 1;
|
|
snd_hda_set_power_save(&chip->bus, power_save * 1000);
|
|
|
|
out_free:
|
|
return; /* no error return from async probe */
|
|
}
|
|
|
|
static int hda_tegra_remove(struct platform_device *pdev)
|
|
{
|
|
return snd_card_free(dev_get_drvdata(&pdev->dev));
|
|
}
|
|
|
|
static void hda_tegra_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct snd_card *card = dev_get_drvdata(&pdev->dev);
|
|
struct azx *chip;
|
|
|
|
if (!card)
|
|
return;
|
|
chip = card->private_data;
|
|
if (chip && chip->running)
|
|
azx_stop_chip(chip);
|
|
}
|
|
|
|
static struct platform_driver tegra_platform_hda = {
|
|
.driver = {
|
|
.name = "tegra-hda",
|
|
.pm = &hda_tegra_pm,
|
|
.of_match_table = hda_tegra_match,
|
|
},
|
|
.probe = hda_tegra_probe,
|
|
.remove = hda_tegra_remove,
|
|
.shutdown = hda_tegra_shutdown,
|
|
};
|
|
module_platform_driver(tegra_platform_hda);
|
|
|
|
MODULE_DESCRIPTION("Tegra HDA bus driver");
|
|
MODULE_LICENSE("GPL v2");
|