284 lines
6.9 KiB
C
284 lines
6.9 KiB
C
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* Copyright (C) 2001 Ralf Baechle
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* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
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* Author: Maciej W. Rozycki <macro@mips.com>
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*
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* This file define the irq handler for MIPS CPU interrupts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* Almost all MIPS CPUs define 8 interrupt sources. They are typically
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* level triggered (i.e., cannot be cleared from CPU; must be cleared from
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* device).
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*
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* The first two are software interrupts (i.e. not exposed as pins) which
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* may be used for IPIs in multi-threaded single-core systems.
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*
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* The last one is usually the CPU timer interrupt if the counter register
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* is present, or for old CPUs with an external FPU by convention it's the
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* FPU exception interrupt.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/setup.h>
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static struct irq_domain *irq_domain;
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static struct irq_domain *ipi_domain;
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static inline void unmask_mips_irq(struct irq_data *d)
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{
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set_c0_status(IE_SW0 << d->hwirq);
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irq_enable_hazard();
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}
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static inline void mask_mips_irq(struct irq_data *d)
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{
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clear_c0_status(IE_SW0 << d->hwirq);
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irq_disable_hazard();
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}
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static struct irq_chip mips_cpu_irq_controller = {
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.name = "MIPS",
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.irq_ack = mask_mips_irq,
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.irq_mask = mask_mips_irq,
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.irq_mask_ack = mask_mips_irq,
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.irq_unmask = unmask_mips_irq,
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.irq_eoi = unmask_mips_irq,
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.irq_disable = mask_mips_irq,
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.irq_enable = unmask_mips_irq,
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};
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/*
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* Basically the same as above but taking care of all the MT stuff
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*/
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static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
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{
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unsigned int vpflags = dvpe();
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clear_c0_cause(C_SW0 << d->hwirq);
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evpe(vpflags);
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unmask_mips_irq(d);
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return 0;
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}
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/*
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* While we ack the interrupt interrupts are disabled and thus we don't need
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* to deal with concurrency issues. Same for mips_cpu_irq_end.
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*/
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static void mips_mt_cpu_irq_ack(struct irq_data *d)
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{
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unsigned int vpflags = dvpe();
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clear_c0_cause(C_SW0 << d->hwirq);
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evpe(vpflags);
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mask_mips_irq(d);
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}
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#ifdef CONFIG_GENERIC_IRQ_IPI
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static void mips_mt_send_ipi(struct irq_data *d, unsigned int cpu)
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{
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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unsigned long flags;
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int vpflags;
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local_irq_save(flags);
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/* We can only send IPIs to VPEs within the local core */
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WARN_ON(cpu_data[cpu].core != current_cpu_data.core);
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vpflags = dvpe();
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settc(cpu_vpe_id(&cpu_data[cpu]));
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write_vpe_c0_cause(read_vpe_c0_cause() | (C_SW0 << hwirq));
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evpe(vpflags);
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local_irq_restore(flags);
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}
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#endif /* CONFIG_GENERIC_IRQ_IPI */
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static struct irq_chip mips_mt_cpu_irq_controller = {
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.name = "MIPS",
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.irq_startup = mips_mt_cpu_irq_startup,
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.irq_ack = mips_mt_cpu_irq_ack,
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.irq_mask = mask_mips_irq,
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.irq_mask_ack = mips_mt_cpu_irq_ack,
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.irq_unmask = unmask_mips_irq,
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.irq_eoi = unmask_mips_irq,
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.irq_disable = mask_mips_irq,
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.irq_enable = unmask_mips_irq,
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#ifdef CONFIG_GENERIC_IRQ_IPI
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.ipi_send_single = mips_mt_send_ipi,
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#endif
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};
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asmlinkage void __weak plat_irq_dispatch(void)
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{
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unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
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unsigned int virq;
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int irq;
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if (!pending) {
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spurious_interrupt();
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return;
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}
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pending >>= CAUSEB_IP;
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while (pending) {
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irq = fls(pending) - 1;
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if (IS_ENABLED(CONFIG_GENERIC_IRQ_IPI) && irq < 2)
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virq = irq_linear_revmap(ipi_domain, irq);
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else
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virq = irq_linear_revmap(irq_domain, irq);
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do_IRQ(virq);
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pending &= ~BIT(irq);
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}
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}
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static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct irq_chip *chip;
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if (hw < 2 && cpu_has_mipsmt) {
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/* Software interrupts are used for MT/CMT IPI */
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chip = &mips_mt_cpu_irq_controller;
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} else {
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chip = &mips_cpu_irq_controller;
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}
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if (cpu_has_vint)
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set_vi_handler(hw, plat_irq_dispatch);
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irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
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return 0;
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}
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static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
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.map = mips_cpu_intc_map,
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.xlate = irq_domain_xlate_onecell,
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};
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#ifdef CONFIG_GENERIC_IRQ_IPI
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struct cpu_ipi_domain_state {
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DECLARE_BITMAP(allocated, 2);
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};
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static int mips_cpu_ipi_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct cpu_ipi_domain_state *state = domain->host_data;
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unsigned int i, hwirq;
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int ret;
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for (i = 0; i < nr_irqs; i++) {
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hwirq = find_first_zero_bit(state->allocated, 2);
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if (hwirq == 2)
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return -EBUSY;
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bitmap_set(state->allocated, hwirq, 1);
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ret = irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq,
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&mips_mt_cpu_irq_controller,
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NULL);
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if (ret)
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return ret;
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ret = irq_set_irq_type(virq + i, IRQ_TYPE_LEVEL_HIGH);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int mips_cpu_ipi_match(struct irq_domain *d, struct device_node *node,
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enum irq_domain_bus_token bus_token)
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{
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bool is_ipi;
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switch (bus_token) {
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case DOMAIN_BUS_IPI:
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is_ipi = d->bus_token == bus_token;
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return (!node || (to_of_node(d->fwnode) == node)) && is_ipi;
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default:
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return 0;
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}
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}
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static const struct irq_domain_ops mips_cpu_ipi_chip_ops = {
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.alloc = mips_cpu_ipi_alloc,
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.match = mips_cpu_ipi_match,
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};
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static void mips_cpu_register_ipi_domain(struct device_node *of_node)
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{
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struct cpu_ipi_domain_state *ipi_domain_state;
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ipi_domain_state = kzalloc(sizeof(*ipi_domain_state), GFP_KERNEL);
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ipi_domain = irq_domain_add_hierarchy(irq_domain,
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IRQ_DOMAIN_FLAG_IPI_SINGLE,
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2, of_node,
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&mips_cpu_ipi_chip_ops,
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ipi_domain_state);
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if (!ipi_domain)
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panic("Failed to add MIPS CPU IPI domain");
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irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
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}
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#else /* !CONFIG_GENERIC_IRQ_IPI */
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static inline void mips_cpu_register_ipi_domain(struct device_node *of_node) {}
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#endif /* !CONFIG_GENERIC_IRQ_IPI */
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static void __init __mips_cpu_irq_init(struct device_node *of_node)
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{
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/* Mask interrupts. */
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clear_c0_status(ST0_IM);
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clear_c0_cause(CAUSEF_IP);
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irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
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&mips_cpu_intc_irq_domain_ops,
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NULL);
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if (!irq_domain)
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panic("Failed to add irqdomain for MIPS CPU");
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/*
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* Only proceed to register the software interrupt IPI implementation
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* for CPUs which implement the MIPS MT (multi-threading) ASE.
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*/
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if (cpu_has_mipsmt)
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mips_cpu_register_ipi_domain(of_node);
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}
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void __init mips_cpu_irq_init(void)
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{
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__mips_cpu_irq_init(NULL);
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}
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int __init mips_cpu_irq_of_init(struct device_node *of_node,
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struct device_node *parent)
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{
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__mips_cpu_irq_init(of_node);
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return 0;
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}
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IRQCHIP_DECLARE(cpu_intc, "mti,cpu-interrupt-controller", mips_cpu_irq_of_init);
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