599 lines
16 KiB
C
599 lines
16 KiB
C
/*
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* intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
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*
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* (C) Copyright 2008-2010 Intel Corporation
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* Author: Sreedhara DS (sreedhara.ds@intel.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*
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* SCU running in ARC processor communicates with other entity running in IA
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* core through IPC mechanism which in turn messaging between IA core ad SCU.
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* SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
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* SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
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* IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
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* along with other APIs.
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*/
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/pm.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/sfi.h>
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#include <linux/module.h>
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#include <asm/mrst.h>
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#include <asm/intel_scu_ipc.h>
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/* IPC defines the following message types */
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#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
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#define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
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#define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
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#define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
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#define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
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/* Command id associated with message IPCMSG_PCNTRL */
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#define IPC_CMD_PCNTRL_W 0 /* Register write */
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#define IPC_CMD_PCNTRL_R 1 /* Register read */
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#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
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/*
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* IPC register summary
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*
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* IPC register blocks are memory mapped at fixed address of 0xFF11C000
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* To read or write information to the SCU, driver writes to IPC-1 memory
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* mapped registers (base address 0xFF11C000). The following is the IPC
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* mechanism
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*
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* 1. IA core cDMI interface claims this transaction and converts it to a
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* Transaction Layer Packet (TLP) message which is sent across the cDMI.
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*
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* 2. South Complex cDMI block receives this message and writes it to
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* the IPC-1 register block, causing an interrupt to the SCU
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*
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* 3. SCU firmware decodes this interrupt and IPC message and the appropriate
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* message handler is called within firmware.
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*/
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#define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */
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#define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */
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#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
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#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
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#define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */
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#define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */
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static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
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static void ipc_remove(struct pci_dev *pdev);
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struct intel_scu_ipc_dev {
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struct pci_dev *pdev;
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void __iomem *ipc_base;
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void __iomem *i2c_base;
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};
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static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
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static int platform; /* Platform type */
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/*
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* IPC Read Buffer (Read Only):
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* 16 byte buffer for receiving data from SCU, if IPC command
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* processing results in response data
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*/
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#define IPC_READ_BUFFER 0x90
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#define IPC_I2C_CNTRL_ADDR 0
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#define I2C_DATA_ADDR 0x04
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static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
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/*
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* Command Register (Write Only):
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* A write to this register results in an interrupt to the SCU core processor
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* Format:
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* |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
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*/
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static inline void ipc_command(u32 cmd) /* Send ipc command */
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{
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writel(cmd, ipcdev.ipc_base);
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}
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/*
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* IPC Write Buffer (Write Only):
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* 16-byte buffer for sending data associated with IPC command to
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* SCU. Size of the data is specified in the IPC_COMMAND_REG register
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*/
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static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
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{
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writel(data, ipcdev.ipc_base + 0x80 + offset);
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}
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/*
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* Status Register (Read Only):
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* Driver will read this register to get the ready/busy status of the IPC
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* block and error status of the IPC command that was just processed by SCU
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* Format:
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* |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
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*/
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static inline u8 ipc_read_status(void)
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{
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return __raw_readl(ipcdev.ipc_base + 0x04);
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}
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static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */
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{
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return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
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}
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static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */
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{
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return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
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}
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static inline int busy_loop(void) /* Wait till scu status is busy */
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{
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u32 status = 0;
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u32 loop_count = 0;
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status = ipc_read_status();
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while (status & 1) {
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udelay(1); /* scu processing time is in few u secods */
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status = ipc_read_status();
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loop_count++;
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/* break if scu doesn't reset busy bit after huge retry */
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if (loop_count > 100000) {
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dev_err(&ipcdev.pdev->dev, "IPC timed out");
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return -ETIMEDOUT;
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}
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}
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if ((status >> 1) & 1)
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return -EIO;
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return 0;
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}
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/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
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static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
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{
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int nc;
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u32 offset = 0;
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int err;
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u8 cbuf[IPC_WWBUF_SIZE] = { };
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u32 *wbuf = (u32 *)&cbuf;
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mutex_lock(&ipclock);
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memset(cbuf, 0, sizeof(cbuf));
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if (ipcdev.pdev == NULL) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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for (nc = 0; nc < count; nc++, offset += 2) {
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cbuf[offset] = addr[nc];
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cbuf[offset + 1] = addr[nc] >> 8;
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}
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if (id == IPC_CMD_PCNTRL_R) {
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for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
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ipc_data_writel(wbuf[nc], offset);
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ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op);
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} else if (id == IPC_CMD_PCNTRL_W) {
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for (nc = 0; nc < count; nc++, offset += 1)
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cbuf[offset] = data[nc];
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for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
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ipc_data_writel(wbuf[nc], offset);
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ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op);
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} else if (id == IPC_CMD_PCNTRL_M) {
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cbuf[offset] = data[0];
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cbuf[offset + 1] = data[1];
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ipc_data_writel(wbuf[0], 0); /* Write wbuff */
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ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
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}
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err = busy_loop();
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if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
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/* Workaround: values are read as 0 without memcpy_fromio */
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memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
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for (nc = 0; nc < count; nc++)
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data[nc] = ipc_data_readb(nc);
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}
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mutex_unlock(&ipclock);
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return err;
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}
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/**
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* intel_scu_ipc_ioread8 - read a word via the SCU
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* @addr: register on SCU
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* @data: return pointer for read byte
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*
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* Read a single register. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_ioread8(u16 addr, u8 *data)
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{
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return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
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}
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EXPORT_SYMBOL(intel_scu_ipc_ioread8);
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/**
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* intel_scu_ipc_ioread16 - read a word via the SCU
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* @addr: register on SCU
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* @data: return pointer for read word
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*
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* Read a register pair. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_ioread16(u16 addr, u16 *data)
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{
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u16 x[2] = {addr, addr + 1 };
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return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
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}
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EXPORT_SYMBOL(intel_scu_ipc_ioread16);
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/**
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* intel_scu_ipc_ioread32 - read a dword via the SCU
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* @addr: register on SCU
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* @data: return pointer for read dword
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*
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* Read four registers. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_ioread32(u16 addr, u32 *data)
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{
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u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
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return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
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}
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EXPORT_SYMBOL(intel_scu_ipc_ioread32);
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/**
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* intel_scu_ipc_iowrite8 - write a byte via the SCU
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* @addr: register on SCU
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* @data: byte to write
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*
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* Write a single register. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_iowrite8(u16 addr, u8 data)
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{
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return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
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}
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EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
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/**
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* intel_scu_ipc_iowrite16 - write a word via the SCU
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* @addr: register on SCU
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* @data: word to write
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*
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* Write two registers. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_iowrite16(u16 addr, u16 data)
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{
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u16 x[2] = {addr, addr + 1 };
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return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
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}
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EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
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/**
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* intel_scu_ipc_iowrite32 - write a dword via the SCU
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* @addr: register on SCU
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* @data: dword to write
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*
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* Write four registers. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_iowrite32(u16 addr, u32 data)
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{
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u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
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return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
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}
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EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
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/**
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* intel_scu_ipc_readvv - read a set of registers
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* @addr: register list
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* @data: bytes to return
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* @len: length of array
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*
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* Read registers. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* The largest array length permitted by the hardware is 5 items.
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*
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* This function may sleep.
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*/
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int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
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{
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return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
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}
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EXPORT_SYMBOL(intel_scu_ipc_readv);
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/**
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* intel_scu_ipc_writev - write a set of registers
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* @addr: register list
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* @data: bytes to write
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* @len: length of array
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*
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* Write registers. Returns 0 on success or an error code. All
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* locking between SCU accesses is handled for the caller.
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*
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* The largest array length permitted by the hardware is 5 items.
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*
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* This function may sleep.
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*
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*/
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int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
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{
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return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
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}
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EXPORT_SYMBOL(intel_scu_ipc_writev);
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/**
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* intel_scu_ipc_update_register - r/m/w a register
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* @addr: register address
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* @bits: bits to update
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* @mask: mask of bits to update
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*
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* Read-modify-write power control unit register. The first data argument
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* must be register value and second is mask value
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* mask is a bitmap that indicates which bits to update.
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* 0 = masked. Don't modify this bit, 1 = modify this bit.
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* returns 0 on success or an error code.
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*
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* This function may sleep. Locking between SCU accesses is handled
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* for the caller.
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*/
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int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
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{
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u8 data[2] = { bits, mask };
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return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
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}
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EXPORT_SYMBOL(intel_scu_ipc_update_register);
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/**
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* intel_scu_ipc_simple_command - send a simple command
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* @cmd: command
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* @sub: sub type
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*
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* Issue a simple command to the SCU. Do not use this interface if
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* you must then access data as any data values may be overwritten
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* by another SCU access by the time this function returns.
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*
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* This function may sleep. Locking for SCU accesses is handled for
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* the caller.
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*/
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int intel_scu_ipc_simple_command(int cmd, int sub)
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{
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int err;
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mutex_lock(&ipclock);
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if (ipcdev.pdev == NULL) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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ipc_command(sub << 12 | cmd);
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err = busy_loop();
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mutex_unlock(&ipclock);
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return err;
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}
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EXPORT_SYMBOL(intel_scu_ipc_simple_command);
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/**
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* intel_scu_ipc_command - command with data
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* @cmd: command
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* @sub: sub type
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* @in: input data
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* @inlen: input length in dwords
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* @out: output data
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* @outlein: output length in dwords
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*
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* Issue a command to the SCU which involves data transfers. Do the
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* data copies under the lock but leave it for the caller to interpret
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*/
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int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
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u32 *out, int outlen)
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{
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int i, err;
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mutex_lock(&ipclock);
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if (ipcdev.pdev == NULL) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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for (i = 0; i < inlen; i++)
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ipc_data_writel(*in++, 4 * i);
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ipc_command((inlen << 16) | (sub << 12) | cmd);
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err = busy_loop();
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for (i = 0; i < outlen; i++)
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*out++ = ipc_data_readl(4 * i);
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mutex_unlock(&ipclock);
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return err;
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}
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EXPORT_SYMBOL(intel_scu_ipc_command);
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/*I2C commands */
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#define IPC_I2C_WRITE 1 /* I2C Write command */
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#define IPC_I2C_READ 2 /* I2C Read command */
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/**
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* intel_scu_ipc_i2c_cntrl - I2C read/write operations
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* @addr: I2C address + command bits
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* @data: data to read/write
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*
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* Perform an an I2C read/write operation via the SCU. All locking is
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* handled for the caller. This function may sleep.
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*
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* Returns an error code or 0 on success.
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*
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* This has to be in the IPC driver for the locking.
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*/
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int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
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{
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u32 cmd = 0;
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mutex_lock(&ipclock);
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if (ipcdev.pdev == NULL) {
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mutex_unlock(&ipclock);
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return -ENODEV;
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}
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cmd = (addr >> 24) & 0xFF;
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if (cmd == IPC_I2C_READ) {
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writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
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/* Write not getting updated without delay */
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mdelay(1);
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*data = readl(ipcdev.i2c_base + I2C_DATA_ADDR);
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} else if (cmd == IPC_I2C_WRITE) {
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writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR);
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mdelay(1);
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writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
|
|
} else {
|
|
dev_err(&ipcdev.pdev->dev,
|
|
"intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
|
|
|
|
mutex_unlock(&ipclock);
|
|
return -EIO;
|
|
}
|
|
mutex_unlock(&ipclock);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
|
|
|
|
/*
|
|
* Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
|
|
* When ioc bit is set to 1, caller api must wait for interrupt handler called
|
|
* which in turn unlocks the caller api. Currently this is not used
|
|
*
|
|
* This is edge triggered so we need take no action to clear anything
|
|
*/
|
|
static irqreturn_t ioc(int irq, void *dev_id)
|
|
{
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/**
|
|
* ipc_probe - probe an Intel SCU IPC
|
|
* @dev: the PCI device matching
|
|
* @id: entry in the match table
|
|
*
|
|
* Enable and install an intel SCU IPC. This appears in the PCI space
|
|
* but uses some hard coded addresses as well.
|
|
*/
|
|
static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
int err;
|
|
resource_size_t pci_resource;
|
|
|
|
if (ipcdev.pdev) /* We support only one SCU */
|
|
return -EBUSY;
|
|
|
|
ipcdev.pdev = pci_dev_get(dev);
|
|
|
|
err = pci_enable_device(dev);
|
|
if (err)
|
|
return err;
|
|
|
|
err = pci_request_regions(dev, "intel_scu_ipc");
|
|
if (err)
|
|
return err;
|
|
|
|
pci_resource = pci_resource_start(dev, 0);
|
|
if (!pci_resource)
|
|
return -ENOMEM;
|
|
|
|
if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
|
|
return -EBUSY;
|
|
|
|
ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR);
|
|
if (!ipcdev.ipc_base)
|
|
return -ENOMEM;
|
|
|
|
ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR);
|
|
if (!ipcdev.i2c_base) {
|
|
iounmap(ipcdev.ipc_base);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
intel_scu_devices_create();
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ipc_remove - remove a bound IPC device
|
|
* @pdev: PCI device
|
|
*
|
|
* In practice the SCU is not removable but this function is also
|
|
* called for each device on a module unload or cleanup which is the
|
|
* path that will get used.
|
|
*
|
|
* Free up the mappings and release the PCI resources
|
|
*/
|
|
static void ipc_remove(struct pci_dev *pdev)
|
|
{
|
|
free_irq(pdev->irq, &ipcdev);
|
|
pci_release_regions(pdev);
|
|
pci_dev_put(ipcdev.pdev);
|
|
iounmap(ipcdev.ipc_base);
|
|
iounmap(ipcdev.i2c_base);
|
|
ipcdev.pdev = NULL;
|
|
intel_scu_devices_destroy();
|
|
}
|
|
|
|
static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
|
|
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)},
|
|
{ 0,}
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, pci_ids);
|
|
|
|
static struct pci_driver ipc_driver = {
|
|
.name = "intel_scu_ipc",
|
|
.id_table = pci_ids,
|
|
.probe = ipc_probe,
|
|
.remove = ipc_remove,
|
|
};
|
|
|
|
|
|
static int __init intel_scu_ipc_init(void)
|
|
{
|
|
platform = mrst_identify_cpu();
|
|
if (platform == 0)
|
|
return -ENODEV;
|
|
return pci_register_driver(&ipc_driver);
|
|
}
|
|
|
|
static void __exit intel_scu_ipc_exit(void)
|
|
{
|
|
pci_unregister_driver(&ipc_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>");
|
|
MODULE_DESCRIPTION("Intel SCU IPC driver");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
module_init(intel_scu_ipc_init);
|
|
module_exit(intel_scu_ipc_exit);
|