572 lines
13 KiB
C
572 lines
13 KiB
C
/*
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* SuperH Timer Support - TMU
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*
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* Copyright (C) 2009 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/sh_timer.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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struct sh_tmu_priv {
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void __iomem *mapbase;
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struct clk *clk;
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struct irqaction irqaction;
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struct platform_device *pdev;
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unsigned long rate;
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unsigned long periodic;
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struct clock_event_device ced;
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struct clocksource cs;
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bool cs_enabled;
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unsigned int enable_count;
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};
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static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
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#define TSTR -1 /* shared register */
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#define TCOR 0 /* channel register */
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#define TCNT 1 /* channel register */
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#define TCR 2 /* channel register */
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static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
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{
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struct sh_timer_config *cfg = p->pdev->dev.platform_data;
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void __iomem *base = p->mapbase;
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unsigned long offs;
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if (reg_nr == TSTR)
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return ioread8(base - cfg->channel_offset);
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offs = reg_nr << 2;
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if (reg_nr == TCR)
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return ioread16(base + offs);
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else
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return ioread32(base + offs);
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}
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static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
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unsigned long value)
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{
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struct sh_timer_config *cfg = p->pdev->dev.platform_data;
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void __iomem *base = p->mapbase;
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unsigned long offs;
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if (reg_nr == TSTR) {
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iowrite8(value, base - cfg->channel_offset);
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return;
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}
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offs = reg_nr << 2;
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if (reg_nr == TCR)
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iowrite16(value, base + offs);
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else
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iowrite32(value, base + offs);
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}
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static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
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{
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struct sh_timer_config *cfg = p->pdev->dev.platform_data;
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unsigned long flags, value;
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/* start stop register shared by multiple timer channels */
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raw_spin_lock_irqsave(&sh_tmu_lock, flags);
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value = sh_tmu_read(p, TSTR);
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if (start)
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value |= 1 << cfg->timer_bit;
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else
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value &= ~(1 << cfg->timer_bit);
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sh_tmu_write(p, TSTR, value);
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raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
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}
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static int __sh_tmu_enable(struct sh_tmu_priv *p)
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{
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int ret;
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/* enable clock */
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ret = clk_enable(p->clk);
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if (ret) {
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dev_err(&p->pdev->dev, "cannot enable clock\n");
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return ret;
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}
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/* make sure channel is disabled */
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sh_tmu_start_stop_ch(p, 0);
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/* maximum timeout */
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sh_tmu_write(p, TCOR, 0xffffffff);
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sh_tmu_write(p, TCNT, 0xffffffff);
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/* configure channel to parent clock / 4, irq off */
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p->rate = clk_get_rate(p->clk) / 4;
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sh_tmu_write(p, TCR, 0x0000);
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/* enable channel */
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sh_tmu_start_stop_ch(p, 1);
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return 0;
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}
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static int sh_tmu_enable(struct sh_tmu_priv *p)
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{
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if (p->enable_count++ > 0)
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return 0;
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pm_runtime_get_sync(&p->pdev->dev);
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dev_pm_syscore_device(&p->pdev->dev, true);
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return __sh_tmu_enable(p);
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}
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static void __sh_tmu_disable(struct sh_tmu_priv *p)
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{
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/* disable channel */
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sh_tmu_start_stop_ch(p, 0);
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/* disable interrupts in TMU block */
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sh_tmu_write(p, TCR, 0x0000);
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/* stop clock */
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clk_disable(p->clk);
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}
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static void sh_tmu_disable(struct sh_tmu_priv *p)
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{
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if (WARN_ON(p->enable_count == 0))
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return;
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if (--p->enable_count > 0)
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return;
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__sh_tmu_disable(p);
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dev_pm_syscore_device(&p->pdev->dev, false);
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pm_runtime_put(&p->pdev->dev);
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}
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static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
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int periodic)
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{
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/* stop timer */
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sh_tmu_start_stop_ch(p, 0);
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/* acknowledge interrupt */
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sh_tmu_read(p, TCR);
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/* enable interrupt */
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sh_tmu_write(p, TCR, 0x0020);
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/* reload delta value in case of periodic timer */
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if (periodic)
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sh_tmu_write(p, TCOR, delta);
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else
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sh_tmu_write(p, TCOR, 0xffffffff);
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sh_tmu_write(p, TCNT, delta);
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/* start timer */
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sh_tmu_start_stop_ch(p, 1);
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}
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static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
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{
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struct sh_tmu_priv *p = dev_id;
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/* disable or acknowledge interrupt */
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if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
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sh_tmu_write(p, TCR, 0x0000);
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else
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sh_tmu_write(p, TCR, 0x0020);
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/* notify clockevent layer */
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p->ced.event_handler(&p->ced);
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return IRQ_HANDLED;
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}
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static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
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{
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return container_of(cs, struct sh_tmu_priv, cs);
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}
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static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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return sh_tmu_read(p, TCNT) ^ 0xffffffff;
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}
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static int sh_tmu_clocksource_enable(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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int ret;
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if (WARN_ON(p->cs_enabled))
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return 0;
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ret = sh_tmu_enable(p);
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if (!ret) {
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__clocksource_updatefreq_hz(cs, p->rate);
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p->cs_enabled = true;
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}
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return ret;
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}
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static void sh_tmu_clocksource_disable(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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if (WARN_ON(!p->cs_enabled))
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return;
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sh_tmu_disable(p);
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p->cs_enabled = false;
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}
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static void sh_tmu_clocksource_suspend(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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if (!p->cs_enabled)
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return;
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if (--p->enable_count == 0) {
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__sh_tmu_disable(p);
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pm_genpd_syscore_poweroff(&p->pdev->dev);
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}
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}
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static void sh_tmu_clocksource_resume(struct clocksource *cs)
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{
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struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
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if (!p->cs_enabled)
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return;
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if (p->enable_count++ == 0) {
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pm_genpd_syscore_poweron(&p->pdev->dev);
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__sh_tmu_enable(p);
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}
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}
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static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
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char *name, unsigned long rating)
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{
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struct clocksource *cs = &p->cs;
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cs->name = name;
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cs->rating = rating;
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cs->read = sh_tmu_clocksource_read;
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cs->enable = sh_tmu_clocksource_enable;
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cs->disable = sh_tmu_clocksource_disable;
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cs->suspend = sh_tmu_clocksource_suspend;
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cs->resume = sh_tmu_clocksource_resume;
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cs->mask = CLOCKSOURCE_MASK(32);
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cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
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dev_info(&p->pdev->dev, "used as clock source\n");
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/* Register with dummy 1 Hz value, gets updated in ->enable() */
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clocksource_register_hz(cs, 1);
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return 0;
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}
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static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
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{
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return container_of(ced, struct sh_tmu_priv, ced);
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}
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static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
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{
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struct clock_event_device *ced = &p->ced;
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sh_tmu_enable(p);
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clockevents_config(ced, p->rate);
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if (periodic) {
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p->periodic = (p->rate + HZ/2) / HZ;
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sh_tmu_set_next(p, p->periodic, 1);
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}
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}
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static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
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struct clock_event_device *ced)
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{
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struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
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int disabled = 0;
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/* deal with old setting first */
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switch (ced->mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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case CLOCK_EVT_MODE_ONESHOT:
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sh_tmu_disable(p);
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disabled = 1;
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break;
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default:
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break;
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}
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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dev_info(&p->pdev->dev, "used for periodic clock events\n");
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sh_tmu_clock_event_start(p, 1);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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dev_info(&p->pdev->dev, "used for oneshot clock events\n");
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sh_tmu_clock_event_start(p, 0);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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if (!disabled)
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sh_tmu_disable(p);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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break;
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}
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}
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static int sh_tmu_clock_event_next(unsigned long delta,
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struct clock_event_device *ced)
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{
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struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
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BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
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/* program new delta value */
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sh_tmu_set_next(p, delta, 0);
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return 0;
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}
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static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
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{
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pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->pdev->dev);
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}
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static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
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{
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pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->pdev->dev);
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}
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static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
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char *name, unsigned long rating)
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{
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struct clock_event_device *ced = &p->ced;
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int ret;
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memset(ced, 0, sizeof(*ced));
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ced->name = name;
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ced->features = CLOCK_EVT_FEAT_PERIODIC;
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ced->features |= CLOCK_EVT_FEAT_ONESHOT;
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ced->rating = rating;
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ced->cpumask = cpumask_of(0);
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ced->set_next_event = sh_tmu_clock_event_next;
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ced->set_mode = sh_tmu_clock_event_mode;
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ced->suspend = sh_tmu_clock_event_suspend;
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ced->resume = sh_tmu_clock_event_resume;
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dev_info(&p->pdev->dev, "used for clock events\n");
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clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
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ret = setup_irq(p->irqaction.irq, &p->irqaction);
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if (ret) {
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dev_err(&p->pdev->dev, "failed to request irq %d\n",
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p->irqaction.irq);
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return;
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}
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}
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static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
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unsigned long clockevent_rating,
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unsigned long clocksource_rating)
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{
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if (clockevent_rating)
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sh_tmu_register_clockevent(p, name, clockevent_rating);
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else if (clocksource_rating)
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sh_tmu_register_clocksource(p, name, clocksource_rating);
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return 0;
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}
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static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
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{
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struct sh_timer_config *cfg = pdev->dev.platform_data;
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struct resource *res;
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int irq, ret;
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ret = -ENXIO;
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memset(p, 0, sizeof(*p));
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p->pdev = pdev;
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if (!cfg) {
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dev_err(&p->pdev->dev, "missing platform data\n");
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goto err0;
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}
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platform_set_drvdata(pdev, p);
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res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&p->pdev->dev, "failed to get I/O memory\n");
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goto err0;
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}
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irq = platform_get_irq(p->pdev, 0);
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if (irq < 0) {
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dev_err(&p->pdev->dev, "failed to get irq\n");
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goto err0;
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}
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/* map memory, let mapbase point to our channel */
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p->mapbase = ioremap_nocache(res->start, resource_size(res));
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if (p->mapbase == NULL) {
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dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
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goto err0;
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}
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/* setup data for setup_irq() (too early for request_irq()) */
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p->irqaction.name = dev_name(&p->pdev->dev);
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p->irqaction.handler = sh_tmu_interrupt;
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p->irqaction.dev_id = p;
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p->irqaction.irq = irq;
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p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
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IRQF_IRQPOLL | IRQF_NOBALANCING;
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/* get hold of clock */
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p->clk = clk_get(&p->pdev->dev, "tmu_fck");
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if (IS_ERR(p->clk)) {
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dev_err(&p->pdev->dev, "cannot get clock\n");
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ret = PTR_ERR(p->clk);
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goto err1;
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}
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ret = clk_prepare(p->clk);
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if (ret < 0)
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goto err2;
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p->cs_enabled = false;
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p->enable_count = 0;
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ret = sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
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cfg->clockevent_rating,
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cfg->clocksource_rating);
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if (ret < 0)
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goto err3;
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return 0;
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err3:
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clk_unprepare(p->clk);
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err2:
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clk_put(p->clk);
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err1:
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iounmap(p->mapbase);
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err0:
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return ret;
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}
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static int sh_tmu_probe(struct platform_device *pdev)
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{
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struct sh_tmu_priv *p = platform_get_drvdata(pdev);
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struct sh_timer_config *cfg = pdev->dev.platform_data;
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int ret;
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if (!is_early_platform_device(pdev)) {
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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}
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if (p) {
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dev_info(&pdev->dev, "kept as earlytimer\n");
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goto out;
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}
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p = kmalloc(sizeof(*p), GFP_KERNEL);
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if (p == NULL) {
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dev_err(&pdev->dev, "failed to allocate driver data\n");
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return -ENOMEM;
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}
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ret = sh_tmu_setup(p, pdev);
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if (ret) {
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kfree(p);
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platform_set_drvdata(pdev, NULL);
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pm_runtime_idle(&pdev->dev);
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return ret;
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}
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if (is_early_platform_device(pdev))
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return 0;
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out:
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if (cfg->clockevent_rating || cfg->clocksource_rating)
|
|
pm_runtime_irq_safe(&pdev->dev);
|
|
else
|
|
pm_runtime_idle(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sh_tmu_remove(struct platform_device *pdev)
|
|
{
|
|
return -EBUSY; /* cannot unregister clockevent and clocksource */
|
|
}
|
|
|
|
static struct platform_driver sh_tmu_device_driver = {
|
|
.probe = sh_tmu_probe,
|
|
.remove = sh_tmu_remove,
|
|
.driver = {
|
|
.name = "sh_tmu",
|
|
}
|
|
};
|
|
|
|
static int __init sh_tmu_init(void)
|
|
{
|
|
return platform_driver_register(&sh_tmu_device_driver);
|
|
}
|
|
|
|
static void __exit sh_tmu_exit(void)
|
|
{
|
|
platform_driver_unregister(&sh_tmu_device_driver);
|
|
}
|
|
|
|
early_platform_init("earlytimer", &sh_tmu_device_driver);
|
|
subsys_initcall(sh_tmu_init);
|
|
module_exit(sh_tmu_exit);
|
|
|
|
MODULE_AUTHOR("Magnus Damm");
|
|
MODULE_DESCRIPTION("SuperH TMU Timer Driver");
|
|
MODULE_LICENSE("GPL v2");
|