360 lines
8.5 KiB
C
360 lines
8.5 KiB
C
/*
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* arch/arm/plat-orion/gpio.c
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*
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* Marvell Orion SoC GPIO handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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static DEFINE_SPINLOCK(gpio_lock);
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static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
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static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
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static inline void __set_direction(unsigned pin, int input)
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{
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u32 u;
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u = readl(GPIO_IO_CONF(pin));
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if (input)
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u |= 1 << (pin & 31);
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else
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u &= ~(1 << (pin & 31));
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writel(u, GPIO_IO_CONF(pin));
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}
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static void __set_level(unsigned pin, int high)
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{
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u32 u;
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u = readl(GPIO_OUT(pin));
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if (high)
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u |= 1 << (pin & 31);
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else
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u &= ~(1 << (pin & 31));
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writel(u, GPIO_OUT(pin));
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}
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static inline void __set_blinking(unsigned pin, int blink)
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{
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u32 u;
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u = readl(GPIO_BLINK_EN(pin));
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if (blink)
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u |= 1 << (pin & 31);
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else
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u &= ~(1 << (pin & 31));
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writel(u, GPIO_BLINK_EN(pin));
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}
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static inline int orion_gpio_is_valid(unsigned pin, int mode)
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{
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if (pin < GPIO_MAX) {
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if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input))
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goto err_out;
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if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, gpio_valid_output))
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goto err_out;
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return true;
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}
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err_out:
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pr_debug("%s: invalid GPIO %d\n", __func__, pin);
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return false;
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}
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/*
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* GENERIC_GPIO primitives.
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*/
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static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
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{
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unsigned long flags;
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if (!orion_gpio_is_valid(pin, GPIO_INPUT_OK))
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return -EINVAL;
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spin_lock_irqsave(&gpio_lock, flags);
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/* Configure GPIO direction. */
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__set_direction(pin, 1);
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spin_unlock_irqrestore(&gpio_lock, flags);
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return 0;
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}
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static int orion_gpio_get_value(struct gpio_chip *chip, unsigned pin)
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{
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int val;
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if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)))
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val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin));
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else
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val = readl(GPIO_OUT(pin));
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return (val >> (pin & 31)) & 1;
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}
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static int orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
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int value)
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{
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unsigned long flags;
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if (!orion_gpio_is_valid(pin, GPIO_OUTPUT_OK))
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return -EINVAL;
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spin_lock_irqsave(&gpio_lock, flags);
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/* Disable blinking. */
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__set_blinking(pin, 0);
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/* Configure GPIO output value. */
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__set_level(pin, value);
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/* Configure GPIO direction. */
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__set_direction(pin, 0);
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spin_unlock_irqrestore(&gpio_lock, flags);
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return 0;
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}
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static void orion_gpio_set_value(struct gpio_chip *chip, unsigned pin,
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int value)
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{
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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/* Configure GPIO output value. */
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__set_level(pin, value);
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spin_unlock_irqrestore(&gpio_lock, flags);
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}
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static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
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{
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if (orion_gpio_is_valid(pin, GPIO_INPUT_OK) ||
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orion_gpio_is_valid(pin, GPIO_OUTPUT_OK))
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return 0;
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return -EINVAL;
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}
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static struct gpio_chip orion_gpiochip = {
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.label = "orion_gpio",
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.direction_input = orion_gpio_direction_input,
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.get = orion_gpio_get_value,
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.direction_output = orion_gpio_direction_output,
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.set = orion_gpio_set_value,
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.request = orion_gpio_request,
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.base = 0,
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.ngpio = GPIO_MAX,
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.can_sleep = 0,
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};
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void __init orion_gpio_init(void)
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{
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gpiochip_add(&orion_gpiochip);
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}
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/*
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* Orion-specific GPIO API extensions.
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*/
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void __init orion_gpio_set_unused(unsigned pin)
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{
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/* Configure as output, drive low. */
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__set_level(pin, 0);
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__set_direction(pin, 0);
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}
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void __init orion_gpio_set_valid(unsigned pin, int mode)
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{
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if (mode == 1)
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mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
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if (mode & GPIO_INPUT_OK)
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__set_bit(pin, gpio_valid_input);
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else
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__clear_bit(pin, gpio_valid_input);
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if (mode & GPIO_OUTPUT_OK)
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__set_bit(pin, gpio_valid_output);
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else
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__clear_bit(pin, gpio_valid_output);
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}
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void orion_gpio_set_blink(unsigned pin, int blink)
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{
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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/* Set output value to zero. */
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__set_level(pin, 0);
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/* Set blinking. */
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__set_blinking(pin, blink);
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spin_unlock_irqrestore(&gpio_lock, flags);
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}
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EXPORT_SYMBOL(orion_gpio_set_blink);
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/*****************************************************************************
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* Orion GPIO IRQ
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*
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* GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
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* value of the line or the opposite value.
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*
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* Level IRQ handlers: DATA_IN is used directly as cause register.
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* Interrupt are masked by LEVEL_MASK registers.
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* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
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* Interrupt are masked by EDGE_MASK registers.
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* Both-edge handlers: Similar to regular Edge handlers, but also swaps
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* the polarity to catch the next line transaction.
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* This is a race condition that might not perfectly
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* work on some use cases.
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*
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* Every eight GPIO lines are grouped (OR'ed) before going up to main
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* cause register.
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*
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* EDGE cause mask
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* data-in /--------| |-----| |----\
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* -----| |----- ---- to main cause reg
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* X \----------------| |----/
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* polarity LEVEL mask
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*
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****************************************************************************/
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static void gpio_irq_ack(u32 irq)
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{
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int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
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int pin = irq_to_gpio(irq);
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writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
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}
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}
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static void gpio_irq_mask(u32 irq)
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{
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int pin = irq_to_gpio(irq);
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int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
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u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
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GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
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u32 u = readl(reg);
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u &= ~(1 << (pin & 31));
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writel(u, reg);
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}
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static void gpio_irq_unmask(u32 irq)
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{
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int pin = irq_to_gpio(irq);
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int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
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u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
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GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
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u32 u = readl(reg);
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u |= 1 << (pin & 31);
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writel(u, reg);
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}
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static int gpio_irq_set_type(u32 irq, u32 type)
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{
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int pin = irq_to_gpio(irq);
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struct irq_desc *desc;
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u32 u;
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u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
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if (!u) {
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printk(KERN_ERR "orion gpio_irq_set_type failed "
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"(irq %d, pin %d).\n", irq, pin);
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return -EINVAL;
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}
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desc = irq_desc + irq;
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/*
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* Set edge/level type.
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*/
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
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desc->handle_irq = handle_edge_irq;
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} else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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desc->handle_irq = handle_level_irq;
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} else {
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printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
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return -EINVAL;
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}
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/*
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* Configure interrupt polarity.
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*/
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if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
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u = readl(GPIO_IN_POL(pin));
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u &= ~(1 << (pin & 31));
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writel(u, GPIO_IN_POL(pin));
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} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
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u = readl(GPIO_IN_POL(pin));
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u |= 1 << (pin & 31);
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writel(u, GPIO_IN_POL(pin));
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} else if (type == IRQ_TYPE_EDGE_BOTH) {
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u32 v;
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v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin));
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/*
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* set initial polarity based on current input level
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*/
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u = readl(GPIO_IN_POL(pin));
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if (v & (1 << (pin & 31)))
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u |= 1 << (pin & 31); /* falling */
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else
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u &= ~(1 << (pin & 31)); /* rising */
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writel(u, GPIO_IN_POL(pin));
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}
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desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;
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return 0;
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}
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struct irq_chip orion_gpio_irq_chip = {
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.name = "orion_gpio_irq",
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.ack = gpio_irq_ack,
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.mask = gpio_irq_mask,
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.unmask = gpio_irq_unmask,
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.set_type = gpio_irq_set_type,
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};
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void orion_gpio_irq_handler(int pinoff)
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{
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u32 cause;
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int pin;
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cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff));
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cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff));
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for (pin = pinoff; pin < pinoff + 8; pin++) {
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int irq = gpio_to_irq(pin);
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struct irq_desc *desc = irq_desc + irq;
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if (!(cause & (1 << (pin & 31))))
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continue;
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if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
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/* Swap polarity (race with GPIO line) */
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u32 polarity;
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polarity = readl(GPIO_IN_POL(pin));
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polarity ^= 1 << (pin & 31);
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writel(polarity, GPIO_IN_POL(pin));
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}
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desc_handle_irq(irq, desc);
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}
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}
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