141 lines
3.7 KiB
ArmAsm
141 lines
3.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Shared glue code for 128bit block ciphers, AVX assembler macros
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*
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* Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
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*/
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#define load_8way(src, x0, x1, x2, x3, x4, x5, x6, x7) \
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vmovdqu (0*16)(src), x0; \
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vmovdqu (1*16)(src), x1; \
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vmovdqu (2*16)(src), x2; \
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vmovdqu (3*16)(src), x3; \
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vmovdqu (4*16)(src), x4; \
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vmovdqu (5*16)(src), x5; \
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vmovdqu (6*16)(src), x6; \
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vmovdqu (7*16)(src), x7;
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#define store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \
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vmovdqu x0, (0*16)(dst); \
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vmovdqu x1, (1*16)(dst); \
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vmovdqu x2, (2*16)(dst); \
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vmovdqu x3, (3*16)(dst); \
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vmovdqu x4, (4*16)(dst); \
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vmovdqu x5, (5*16)(dst); \
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vmovdqu x6, (6*16)(dst); \
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vmovdqu x7, (7*16)(dst);
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#define store_cbc_8way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \
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vpxor (0*16)(src), x1, x1; \
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vpxor (1*16)(src), x2, x2; \
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vpxor (2*16)(src), x3, x3; \
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vpxor (3*16)(src), x4, x4; \
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vpxor (4*16)(src), x5, x5; \
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vpxor (5*16)(src), x6, x6; \
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vpxor (6*16)(src), x7, x7; \
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store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
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#define inc_le128(x, minus_one, tmp) \
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vpcmpeqq minus_one, x, tmp; \
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vpsubq minus_one, x, x; \
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vpslldq $8, tmp, tmp; \
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vpsubq tmp, x, x;
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#define load_ctr_8way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2) \
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vpcmpeqd t0, t0, t0; \
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vpsrldq $8, t0, t0; /* low: -1, high: 0 */ \
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vmovdqa bswap, t1; \
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\
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/* load IV and byteswap */ \
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vmovdqu (iv), x7; \
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vpshufb t1, x7, x0; \
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\
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/* construct IVs */ \
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inc_le128(x7, t0, t2); \
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vpshufb t1, x7, x1; \
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inc_le128(x7, t0, t2); \
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vpshufb t1, x7, x2; \
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inc_le128(x7, t0, t2); \
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vpshufb t1, x7, x3; \
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inc_le128(x7, t0, t2); \
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vpshufb t1, x7, x4; \
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inc_le128(x7, t0, t2); \
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vpshufb t1, x7, x5; \
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inc_le128(x7, t0, t2); \
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vpshufb t1, x7, x6; \
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inc_le128(x7, t0, t2); \
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vmovdqa x7, t2; \
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vpshufb t1, x7, x7; \
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inc_le128(t2, t0, t1); \
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vmovdqu t2, (iv);
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#define store_ctr_8way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \
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vpxor (0*16)(src), x0, x0; \
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vpxor (1*16)(src), x1, x1; \
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vpxor (2*16)(src), x2, x2; \
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vpxor (3*16)(src), x3, x3; \
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vpxor (4*16)(src), x4, x4; \
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vpxor (5*16)(src), x5, x5; \
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vpxor (6*16)(src), x6, x6; \
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vpxor (7*16)(src), x7, x7; \
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store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
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#define gf128mul_x_ble(iv, mask, tmp) \
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vpsrad $31, iv, tmp; \
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vpaddq iv, iv, iv; \
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vpshufd $0x13, tmp, tmp; \
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vpand mask, tmp, tmp; \
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vpxor tmp, iv, iv;
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#define load_xts_8way(iv, src, dst, x0, x1, x2, x3, x4, x5, x6, x7, tiv, t0, \
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t1, xts_gf128mul_and_shl1_mask) \
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vmovdqa xts_gf128mul_and_shl1_mask, t0; \
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\
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/* load IV */ \
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vmovdqu (iv), tiv; \
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vpxor (0*16)(src), tiv, x0; \
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vmovdqu tiv, (0*16)(dst); \
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\
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/* construct and store IVs, also xor with source */ \
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gf128mul_x_ble(tiv, t0, t1); \
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vpxor (1*16)(src), tiv, x1; \
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vmovdqu tiv, (1*16)(dst); \
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\
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gf128mul_x_ble(tiv, t0, t1); \
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vpxor (2*16)(src), tiv, x2; \
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vmovdqu tiv, (2*16)(dst); \
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\
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gf128mul_x_ble(tiv, t0, t1); \
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vpxor (3*16)(src), tiv, x3; \
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vmovdqu tiv, (3*16)(dst); \
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\
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gf128mul_x_ble(tiv, t0, t1); \
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vpxor (4*16)(src), tiv, x4; \
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vmovdqu tiv, (4*16)(dst); \
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\
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gf128mul_x_ble(tiv, t0, t1); \
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vpxor (5*16)(src), tiv, x5; \
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vmovdqu tiv, (5*16)(dst); \
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\
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gf128mul_x_ble(tiv, t0, t1); \
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vpxor (6*16)(src), tiv, x6; \
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vmovdqu tiv, (6*16)(dst); \
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\
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gf128mul_x_ble(tiv, t0, t1); \
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vpxor (7*16)(src), tiv, x7; \
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vmovdqu tiv, (7*16)(dst); \
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\
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gf128mul_x_ble(tiv, t0, t1); \
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vmovdqu tiv, (iv);
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#define store_xts_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \
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vpxor (0*16)(dst), x0, x0; \
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vpxor (1*16)(dst), x1, x1; \
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vpxor (2*16)(dst), x2, x2; \
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vpxor (3*16)(dst), x3, x3; \
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vpxor (4*16)(dst), x4, x4; \
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vpxor (5*16)(dst), x5, x5; \
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vpxor (6*16)(dst), x6, x6; \
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vpxor (7*16)(dst), x7, x7; \
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store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
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