387 lines
8.8 KiB
C
387 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/clkdev.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/clk/tegra.h>
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#include <linux/reset-controller.h>
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#include <soc/tegra/fuse.h>
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#include "clk.h"
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/* Global data of Tegra CPU CAR ops */
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static struct tegra_cpu_car_ops dummy_car_ops;
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struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
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int *periph_clk_enb_refcnt;
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static int periph_banks;
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static u32 *periph_state_ctx;
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static struct clk **clks;
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static int clk_num;
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static struct clk_onecell_data clk_data;
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/* Handlers for SoC-specific reset lines */
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static int (*special_reset_assert)(unsigned long);
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static int (*special_reset_deassert)(unsigned long);
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static unsigned int num_special_reset;
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static const struct tegra_clk_periph_regs periph_regs[] = {
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[0] = {
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.enb_reg = CLK_OUT_ENB_L,
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.enb_set_reg = CLK_OUT_ENB_SET_L,
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.enb_clr_reg = CLK_OUT_ENB_CLR_L,
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.rst_reg = RST_DEVICES_L,
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.rst_set_reg = RST_DEVICES_SET_L,
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.rst_clr_reg = RST_DEVICES_CLR_L,
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},
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[1] = {
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.enb_reg = CLK_OUT_ENB_H,
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.enb_set_reg = CLK_OUT_ENB_SET_H,
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.enb_clr_reg = CLK_OUT_ENB_CLR_H,
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.rst_reg = RST_DEVICES_H,
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.rst_set_reg = RST_DEVICES_SET_H,
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.rst_clr_reg = RST_DEVICES_CLR_H,
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},
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[2] = {
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.enb_reg = CLK_OUT_ENB_U,
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.enb_set_reg = CLK_OUT_ENB_SET_U,
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.enb_clr_reg = CLK_OUT_ENB_CLR_U,
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.rst_reg = RST_DEVICES_U,
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.rst_set_reg = RST_DEVICES_SET_U,
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.rst_clr_reg = RST_DEVICES_CLR_U,
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},
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[3] = {
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.enb_reg = CLK_OUT_ENB_V,
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.enb_set_reg = CLK_OUT_ENB_SET_V,
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.enb_clr_reg = CLK_OUT_ENB_CLR_V,
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.rst_reg = RST_DEVICES_V,
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.rst_set_reg = RST_DEVICES_SET_V,
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.rst_clr_reg = RST_DEVICES_CLR_V,
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},
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[4] = {
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.enb_reg = CLK_OUT_ENB_W,
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.enb_set_reg = CLK_OUT_ENB_SET_W,
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.enb_clr_reg = CLK_OUT_ENB_CLR_W,
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.rst_reg = RST_DEVICES_W,
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.rst_set_reg = RST_DEVICES_SET_W,
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.rst_clr_reg = RST_DEVICES_CLR_W,
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},
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[5] = {
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.enb_reg = CLK_OUT_ENB_X,
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.enb_set_reg = CLK_OUT_ENB_SET_X,
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.enb_clr_reg = CLK_OUT_ENB_CLR_X,
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.rst_reg = RST_DEVICES_X,
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.rst_set_reg = RST_DEVICES_SET_X,
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.rst_clr_reg = RST_DEVICES_CLR_X,
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},
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[6] = {
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.enb_reg = CLK_OUT_ENB_Y,
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.enb_set_reg = CLK_OUT_ENB_SET_Y,
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.enb_clr_reg = CLK_OUT_ENB_CLR_Y,
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.rst_reg = RST_DEVICES_Y,
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.rst_set_reg = RST_DEVICES_SET_Y,
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.rst_clr_reg = RST_DEVICES_CLR_Y,
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},
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};
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static void __iomem *clk_base;
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static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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/*
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* If peripheral is on the APB bus then we must read the APB bus to
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* flush the write operation in apb bus. This will avoid peripheral
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* access after disabling clock. Since the reset driver has no
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* knowledge of which reset IDs represent which devices, simply do
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* this all the time.
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*/
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tegra_read_chipid();
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if (id < periph_banks * 32) {
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writel_relaxed(BIT(id % 32),
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clk_base + periph_regs[id / 32].rst_set_reg);
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return 0;
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} else if (id < periph_banks * 32 + num_special_reset) {
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return special_reset_assert(id);
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}
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return -EINVAL;
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}
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static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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if (id < periph_banks * 32) {
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writel_relaxed(BIT(id % 32),
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clk_base + periph_regs[id / 32].rst_clr_reg);
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return 0;
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} else if (id < periph_banks * 32 + num_special_reset) {
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return special_reset_deassert(id);
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}
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return -EINVAL;
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}
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static int tegra_clk_rst_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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int err;
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err = tegra_clk_rst_assert(rcdev, id);
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if (err)
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return err;
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udelay(1);
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return tegra_clk_rst_deassert(rcdev, id);
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}
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const struct tegra_clk_periph_regs *get_reg_bank(int clkid)
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{
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int reg_bank = clkid / 32;
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if (reg_bank < periph_banks)
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return &periph_regs[reg_bank];
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else {
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WARN_ON(1);
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return NULL;
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}
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}
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void tegra_clk_set_pllp_out_cpu(bool enable)
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{
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u32 val;
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val = readl_relaxed(clk_base + CLK_OUT_ENB_Y);
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if (enable)
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val |= CLK_ENB_PLLP_OUT_CPU;
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else
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val &= ~CLK_ENB_PLLP_OUT_CPU;
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writel_relaxed(val, clk_base + CLK_OUT_ENB_Y);
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}
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void tegra_clk_periph_suspend(void)
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{
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unsigned int i, idx;
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idx = 0;
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for (i = 0; i < periph_banks; i++, idx++)
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periph_state_ctx[idx] =
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readl_relaxed(clk_base + periph_regs[i].enb_reg);
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for (i = 0; i < periph_banks; i++, idx++)
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periph_state_ctx[idx] =
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readl_relaxed(clk_base + periph_regs[i].rst_reg);
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}
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void tegra_clk_periph_resume(void)
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{
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unsigned int i, idx;
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idx = 0;
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for (i = 0; i < periph_banks; i++, idx++)
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writel_relaxed(periph_state_ctx[idx],
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clk_base + periph_regs[i].enb_reg);
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/*
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* All non-boot peripherals will be in reset state on resume.
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* Wait for 5us of reset propagation delay before de-asserting
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* the peripherals based on the saved context.
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*/
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fence_udelay(5, clk_base);
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for (i = 0; i < periph_banks; i++, idx++)
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writel_relaxed(periph_state_ctx[idx],
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clk_base + periph_regs[i].rst_reg);
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fence_udelay(2, clk_base);
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}
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static int tegra_clk_periph_ctx_init(int banks)
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{
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periph_state_ctx = kcalloc(2 * banks, sizeof(*periph_state_ctx),
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GFP_KERNEL);
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if (!periph_state_ctx)
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return -ENOMEM;
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return 0;
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}
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struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
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{
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clk_base = regs;
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if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
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return NULL;
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periph_clk_enb_refcnt = kcalloc(32 * banks,
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sizeof(*periph_clk_enb_refcnt),
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GFP_KERNEL);
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if (!periph_clk_enb_refcnt)
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return NULL;
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periph_banks = banks;
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clks = kcalloc(num, sizeof(struct clk *), GFP_KERNEL);
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if (!clks) {
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kfree(periph_clk_enb_refcnt);
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return NULL;
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}
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clk_num = num;
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if (IS_ENABLED(CONFIG_PM_SLEEP)) {
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if (tegra_clk_periph_ctx_init(banks)) {
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kfree(periph_clk_enb_refcnt);
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kfree(clks);
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return NULL;
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}
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}
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return clks;
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}
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void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
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struct clk *clks[], int clk_max)
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{
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struct clk *clk;
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for (; dup_list->clk_id < clk_max; dup_list++) {
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clk = clks[dup_list->clk_id];
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dup_list->lookup.clk = clk;
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clkdev_add(&dup_list->lookup);
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}
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}
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void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
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struct clk *clks[], int clk_max)
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{
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struct clk *clk;
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for (; tbl->clk_id < clk_max; tbl++) {
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clk = clks[tbl->clk_id];
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if (IS_ERR_OR_NULL(clk)) {
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pr_err("%s: invalid entry %ld in clks array for id %d\n",
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__func__, PTR_ERR(clk), tbl->clk_id);
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WARN_ON(1);
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continue;
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}
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if (tbl->parent_id < clk_max) {
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struct clk *parent = clks[tbl->parent_id];
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if (clk_set_parent(clk, parent)) {
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pr_err("%s: Failed to set parent %s of %s\n",
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__func__, __clk_get_name(parent),
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__clk_get_name(clk));
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WARN_ON(1);
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}
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}
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if (tbl->rate)
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if (clk_set_rate(clk, tbl->rate)) {
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pr_err("%s: Failed to set rate %lu of %s\n",
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__func__, tbl->rate,
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__clk_get_name(clk));
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WARN_ON(1);
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}
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if (tbl->state)
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if (clk_prepare_enable(clk)) {
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pr_err("%s: Failed to enable %s\n", __func__,
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__clk_get_name(clk));
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WARN_ON(1);
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}
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}
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}
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static const struct reset_control_ops rst_ops = {
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.assert = tegra_clk_rst_assert,
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.deassert = tegra_clk_rst_deassert,
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.reset = tegra_clk_rst_reset,
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};
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static struct reset_controller_dev rst_ctlr = {
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.ops = &rst_ops,
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.owner = THIS_MODULE,
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.of_reset_n_cells = 1,
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};
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void __init tegra_add_of_provider(struct device_node *np,
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void *clk_src_onecell_get)
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{
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int i;
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for (i = 0; i < clk_num; i++) {
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if (IS_ERR(clks[i])) {
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pr_err
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("Tegra clk %d: register failed with %ld\n",
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i, PTR_ERR(clks[i]));
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}
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if (!clks[i])
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clks[i] = ERR_PTR(-EINVAL);
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}
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clk_data.clks = clks;
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clk_data.clk_num = clk_num;
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of_clk_add_provider(np, clk_src_onecell_get, &clk_data);
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rst_ctlr.of_node = np;
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rst_ctlr.nr_resets = periph_banks * 32 + num_special_reset;
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reset_controller_register(&rst_ctlr);
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}
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void __init tegra_init_special_resets(unsigned int num,
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int (*assert)(unsigned long),
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int (*deassert)(unsigned long))
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{
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num_special_reset = num;
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special_reset_assert = assert;
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special_reset_deassert = deassert;
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}
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void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
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{
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int i;
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for (i = 0; i < num; i++, dev_clks++)
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clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id,
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dev_clks->dev_id);
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for (i = 0; i < clk_num; i++) {
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if (!IS_ERR_OR_NULL(clks[i]))
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clk_register_clkdev(clks[i], __clk_get_name(clks[i]),
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"tegra-clk-debug");
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}
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}
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struct clk ** __init tegra_lookup_dt_id(int clk_id,
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struct tegra_clk *tegra_clk)
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{
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if (tegra_clk[clk_id].present)
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return &clks[tegra_clk[clk_id].dt_id];
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else
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return NULL;
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}
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tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
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static int __init tegra_clocks_apply_init_table(void)
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{
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if (!tegra_clk_apply_init_table)
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return 0;
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tegra_clk_apply_init_table();
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return 0;
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}
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arch_initcall(tegra_clocks_apply_init_table);
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