396 lines
8.9 KiB
C
396 lines
8.9 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/528x/config.c
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*
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* Sub-architcture dependant initialization code for the Motorola
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* 5280 and 5282 CPUs.
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*
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* Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/io.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfqspi.h>
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#ifdef CONFIG_MTD_PARTITIONS
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#include <linux/mtd/partitions.h>
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#endif
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/***************************************************************************/
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void coldfire_reset(void);
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static void coldfire_qspi_cs_control(u8 cs, u8 command);
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/***************************************************************************/
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#if defined(CONFIG_SPI)
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#if defined(CONFIG_WILDFIRE)
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#define SPI_NUM_CHIPSELECTS 0x02
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#define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */
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#define SPI_CS_MASK 0x18
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#define FLASH_BLOCKSIZE (1024*64)
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#define FLASH_NUMBLOCKS 16
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#define FLASH_TYPE "m25p80"
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#define M25P80_CS 0
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#define MMC_CS 1
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#ifdef CONFIG_MTD_PARTITIONS
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static struct mtd_partition stm25p_partitions[] = {
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/* sflash */
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[0] = {
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.name = "stm25p80",
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.offset = 0x00000000,
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.size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS,
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.mask_flags = 0
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}
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};
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#endif
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#elif defined(CONFIG_WILDFIREMOD)
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#define SPI_NUM_CHIPSELECTS 0x08
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#define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */
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#define SPI_CS_MASK 0x78
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#define FLASH_BLOCKSIZE (1024*64)
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#define FLASH_NUMBLOCKS 64
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#define FLASH_TYPE "m25p32"
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/* Reserve 1M for the kernel parition */
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#define FLASH_KERNEL_SIZE (1024 * 1024)
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#define M25P80_CS 5
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#define MMC_CS 6
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#ifdef CONFIG_MTD_PARTITIONS
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static struct mtd_partition stm25p_partitions[] = {
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/* sflash */
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[0] = {
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.name = "kernel",
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.offset = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE,
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.size = FLASH_KERNEL_SIZE,
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.mask_flags = 0
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},
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[1] = {
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.name = "image",
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.offset = 0x00000000,
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.size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE,
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.mask_flags = 0
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},
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[2] = {
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.name = "all",
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.offset = 0x00000000,
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.size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS,
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.mask_flags = 0
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}
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};
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#endif
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#else
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#define SPI_NUM_CHIPSELECTS 0x04
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#define SPI_PAR_VAL 0x7F /* Enable DIN, DOUT, CLK, CS0 - CS4 */
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#endif
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#ifdef MMC_CS
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static struct coldfire_spi_chip flash_chip_info = {
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.mode = SPI_MODE_0,
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.bits_per_word = 16,
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.del_cs_to_clk = 17,
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.del_after_trans = 1,
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.void_write_data = 0
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};
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static struct coldfire_spi_chip mmc_chip_info = {
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.mode = SPI_MODE_0,
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.bits_per_word = 16,
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.del_cs_to_clk = 17,
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.del_after_trans = 1,
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.void_write_data = 0xFFFF
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};
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#endif
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#ifdef M25P80_CS
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static struct flash_platform_data stm25p80_platform_data = {
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.name = "ST M25P80 SPI Flash chip",
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#ifdef CONFIG_MTD_PARTITIONS
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.parts = stm25p_partitions,
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.nr_parts = sizeof(stm25p_partitions) / sizeof(*stm25p_partitions),
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#endif
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.type = FLASH_TYPE
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};
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#endif
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static struct spi_board_info spi_board_info[] __initdata = {
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#ifdef M25P80_CS
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{
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.modalias = "m25p80",
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.max_speed_hz = 16000000,
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.bus_num = 1,
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.chip_select = M25P80_CS,
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.platform_data = &stm25p80_platform_data,
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.controller_data = &flash_chip_info
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},
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#endif
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#ifdef MMC_CS
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{
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.modalias = "mmc_spi",
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.max_speed_hz = 16000000,
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.bus_num = 1,
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.chip_select = MMC_CS,
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.controller_data = &mmc_chip_info
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}
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#endif
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};
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static struct coldfire_spi_master coldfire_master_info = {
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.bus_num = 1,
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.num_chipselect = SPI_NUM_CHIPSELECTS,
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.irq_source = MCF5282_QSPI_IRQ_SOURCE,
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.irq_vector = MCF5282_QSPI_IRQ_VECTOR,
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.irq_mask = ((0x01 << MCF5282_QSPI_IRQ_SOURCE) | 0x01),
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.irq_lp = 0x2B, /* Level 5 and Priority 3 */
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.par_val = SPI_PAR_VAL,
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.cs_control = coldfire_qspi_cs_control,
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};
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static struct resource coldfire_spi_resources[] = {
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[0] = {
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.name = "qspi-par",
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.start = MCF5282_QSPI_PAR,
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.end = MCF5282_QSPI_PAR,
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.flags = IORESOURCE_MEM
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},
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[1] = {
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.name = "qspi-module",
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.start = MCF5282_QSPI_QMR,
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.end = MCF5282_QSPI_QMR + 0x18,
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.flags = IORESOURCE_MEM
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},
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[2] = {
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.name = "qspi-int-level",
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.start = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE,
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.end = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE,
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.flags = IORESOURCE_MEM
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},
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[3] = {
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.name = "qspi-int-mask",
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.start = MCF5282_INTC0 + MCFINTC_IMRL,
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.end = MCF5282_INTC0 + MCFINTC_IMRL,
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.flags = IORESOURCE_MEM
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}
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};
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static struct platform_device coldfire_spi = {
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.name = "spi_coldfire",
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.id = -1,
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.resource = coldfire_spi_resources,
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.num_resources = ARRAY_SIZE(coldfire_spi_resources),
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.dev = {
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.platform_data = &coldfire_master_info,
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}
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};
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static void coldfire_qspi_cs_control(u8 cs, u8 command)
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{
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u8 cs_bit = ((0x01 << cs) << 3) & SPI_CS_MASK;
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#if defined(CONFIG_WILDFIRE)
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u8 cs_mask = ~(((0x01 << cs) << 3) & SPI_CS_MASK);
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#endif
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#if defined(CONFIG_WILDFIREMOD)
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u8 cs_mask = (cs << 3) & SPI_CS_MASK;
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#endif
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/*
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* Don't do anything if the chip select is not
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* one of the port qs pins.
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*/
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if (command & QSPI_CS_INIT) {
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#if defined(CONFIG_WILDFIRE)
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MCF5282_GPIO_DDRQS |= cs_bit;
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MCF5282_GPIO_PQSPAR &= ~cs_bit;
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#endif
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#if defined(CONFIG_WILDFIREMOD)
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MCF5282_GPIO_DDRQS |= SPI_CS_MASK;
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MCF5282_GPIO_PQSPAR &= ~SPI_CS_MASK;
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#endif
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}
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if (command & QSPI_CS_ASSERT) {
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MCF5282_GPIO_PORTQS &= ~SPI_CS_MASK;
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MCF5282_GPIO_PORTQS |= cs_mask;
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} else if (command & QSPI_CS_DROP) {
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MCF5282_GPIO_PORTQS |= SPI_CS_MASK;
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}
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}
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static int __init spi_dev_init(void)
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{
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int retval;
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retval = platform_device_register(&coldfire_spi);
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if (retval < 0)
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return retval;
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if (ARRAY_SIZE(spi_board_info))
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retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
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return retval;
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}
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#endif /* CONFIG_SPI */
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/***************************************************************************/
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static struct mcf_platform_uart m528x_uart_platform[] = {
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{
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.mapbase = MCF_MBAR + MCFUART_BASE1,
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.irq = MCFINT_VECBASE + MCFINT_UART0,
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},
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{
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.mapbase = MCF_MBAR + MCFUART_BASE2,
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.irq = MCFINT_VECBASE + MCFINT_UART0 + 1,
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},
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{
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.mapbase = MCF_MBAR + MCFUART_BASE3,
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.irq = MCFINT_VECBASE + MCFINT_UART0 + 2,
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},
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{ },
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};
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static struct platform_device m528x_uart = {
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.name = "mcfuart",
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.id = 0,
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.dev.platform_data = m528x_uart_platform,
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};
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static struct platform_device *m528x_devices[] __initdata = {
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&m528x_uart,
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};
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/***************************************************************************/
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#define INTC0 (MCF_MBAR + MCFICM_INTC0)
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static void __init m528x_uart_init_line(int line, int irq)
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{
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u8 port;
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u32 imr;
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if ((line < 0) || (line > 2))
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return;
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/* level 6, line based priority */
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writeb(0x30+line, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line);
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imr = readl(INTC0 + MCFINTC_IMRL);
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imr &= ~((1 << (irq - MCFINT_VECBASE)) | 1);
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writel(imr, INTC0 + MCFINTC_IMRL);
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/* make sure PUAPAR is set for UART0 and UART1 */
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if (line < 2) {
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port = readb(MCF_MBAR + MCF5282_GPIO_PUAPAR);
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port |= (0x03 << (line * 2));
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writeb(port, MCF_MBAR + MCF5282_GPIO_PUAPAR);
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}
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}
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static void __init m528x_uarts_init(void)
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{
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const int nrlines = ARRAY_SIZE(m528x_uart_platform);
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int line;
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for (line = 0; (line < nrlines); line++)
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m528x_uart_init_line(line, m528x_uart_platform[line].irq);
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}
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/***************************************************************************/
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void mcf_disableall(void)
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{
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*((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
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*((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL)) = 0xffffffff;
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}
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/***************************************************************************/
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void mcf_autovector(unsigned int vec)
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{
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/* Everything is auto-vectored on the 5272 */
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}
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/***************************************************************************/
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#ifdef CONFIG_WILDFIRE
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void wildfire_halt(void)
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{
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writeb(0, 0x30000007);
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writeb(0x2, 0x30000007);
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}
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#endif
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#ifdef CONFIG_WILDFIREMOD
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void wildfiremod_halt(void)
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{
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printk(KERN_INFO "WildFireMod hibernating...\n");
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/* Set portE.5 to Digital IO */
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MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2));
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/* Make portE.5 an output */
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MCF5282_GPIO_DDRE |= (1 << 5);
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/* Now toggle portE.5 from low to high */
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MCF5282_GPIO_PORTE &= ~(1 << 5);
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MCF5282_GPIO_PORTE |= (1 << 5);
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printk(KERN_EMERG "Failed to hibernate. Halting!\n");
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}
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#endif
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void __init config_BSP(char *commandp, int size)
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{
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mcf_disableall();
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#ifdef CONFIG_WILDFIRE
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mach_halt = wildfire_halt;
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#endif
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#ifdef CONFIG_WILDFIREMOD
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mach_halt = wildfiremod_halt;
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#endif
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}
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/***************************************************************************/
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static int __init init_BSP(void)
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{
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m528x_uarts_init();
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platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices));
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return 0;
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}
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arch_initcall(init_BSP);
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/***************************************************************************/
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