Chandrakala Chavva 7716e6548a Octeon: Fix interrupt irq settings for performance counters. ... Octeon uses different interrupt irq for timer and performance counters. Set CvmCtl[IPPCI] to correct irq value very early. Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com> Patchwork: https://patchwork.linux-mips.org/patch/2085/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2011-05-19 09:55:49 +01:00
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asm	Octeon: Fix interrupt irq settings for performance counters.	2011-05-19 09:55:49 +01:00