209 lines
6.8 KiB
Plaintext
209 lines
6.8 KiB
Plaintext
* Freescale DMA Controllers
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** Freescale Elo DMA Controller
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This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
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series chips such as mpc8315, mpc8349, mpc8379 etc.
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Required properties:
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- compatible : must include "fsl,elo-dma"
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- reg : DMA General Status Register, i.e. DGSR which contains
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status for all the 4 DMA channels
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- ranges : describes the mapping between the address space of the
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DMA channels and the address space of the DMA controller
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- cell-index : controller index. 0 for controller @ 0x8100
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- interrupts : interrupt specifier for DMA IRQ
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- interrupt-parent : optional, if needed for interrupt mapping
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- DMA channel nodes:
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- compatible : must include "fsl,elo-dma-channel"
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However, see note below.
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- reg : DMA channel specific registers
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- cell-index : DMA channel index starts at 0.
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Optional properties:
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- interrupts : interrupt specifier for DMA channel IRQ
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(on 83xx this is expected to be identical to
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the interrupts property of the parent node)
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- interrupt-parent : optional, if needed for interrupt mapping
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Example:
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a4>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <0>;
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reg = <0 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <1>;
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reg = <0x80 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <2>;
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reg = <0x100 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <3>;
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reg = <0x180 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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};
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** Freescale EloPlus DMA Controller
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This is a 4-channel DMA controller with extended addresses and chaining,
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mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
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mpc8540, mpc8641 p4080, bsc9131 etc.
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Required properties:
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- compatible : must include "fsl,eloplus-dma"
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- reg : DMA General Status Register, i.e. DGSR which contains
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status for all the 4 DMA channels
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- cell-index : controller index. 0 for controller @ 0x21000,
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1 for controller @ 0xc000
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- ranges : describes the mapping between the address space of the
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DMA channels and the address space of the DMA controller
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- DMA channel nodes:
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- compatible : must include "fsl,eloplus-dma-channel"
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However, see note below.
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- cell-index : DMA channel index starts at 0.
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- reg : DMA channel specific registers
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- interrupts : interrupt specifier for DMA channel IRQ
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- interrupt-parent : optional, if needed for interrupt mapping
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Example:
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
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reg = <0x21300 4>;
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ranges = <0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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** Freescale Elo3 DMA Controller
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DMA controller which has same function as EloPlus except that Elo3 has 8
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channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
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series chips, such as t1040, t4240, b4860.
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Required properties:
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- compatible : must include "fsl,elo3-dma"
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- reg : contains two entries for DMA General Status Registers,
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i.e. DGSR0 which includes status for channel 1~4, and
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DGSR1 for channel 5~8
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- ranges : describes the mapping between the address space of the
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DMA channels and the address space of the DMA controller
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- DMA channel nodes:
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- compatible : must include "fsl,eloplus-dma-channel"
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- reg : DMA channel specific registers
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- interrupts : interrupt specifier for DMA channel IRQ
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- interrupt-parent : optional, if needed for interrupt mapping
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Example:
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dma@100300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,elo3-dma";
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reg = <0x100300 0x4>,
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<0x100600 0x4>;
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ranges = <0x0 0x100100 0x500>;
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dma-channel@0 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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interrupts = <28 2 0 0>;
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};
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dma-channel@80 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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interrupts = <29 2 0 0>;
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};
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dma-channel@100 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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interrupts = <30 2 0 0>;
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};
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dma-channel@180 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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interrupts = <31 2 0 0>;
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};
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dma-channel@300 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x300 0x80>;
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interrupts = <76 2 0 0>;
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};
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dma-channel@380 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x380 0x80>;
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interrupts = <77 2 0 0>;
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};
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dma-channel@400 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x400 0x80>;
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interrupts = <78 2 0 0>;
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};
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dma-channel@480 {
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compatible = "fsl,eloplus-dma-channel";
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reg = <0x480 0x80>;
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interrupts = <79 2 0 0>;
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};
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};
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Note on DMA channel compatible properties: The compatible property must say
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"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
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driver (fsldma). Any DMA channel used by fsldma cannot be used by another
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DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
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channel that should be used for another driver should not use
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"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
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example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
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for more information.
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