435 lines
13 KiB
C
435 lines
13 KiB
C
/*
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* SCOM support for A2 platforms
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*
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* Copyright 2007-2011 Benjamin Herrenschmidt, David Gibson,
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* Michael Ellerman, IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/cpumask.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <asm/cputhreads.h>
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#include <asm/reg_a2.h>
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#include <asm/scom.h>
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#include <asm/udbg.h>
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#include "wsp.h"
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#define SCOM_RAMC 0x2a /* Ram Command */
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#define SCOM_RAMC_TGT1_EXT 0x80000000
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#define SCOM_RAMC_SRC1_EXT 0x40000000
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#define SCOM_RAMC_SRC2_EXT 0x20000000
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#define SCOM_RAMC_SRC3_EXT 0x10000000
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#define SCOM_RAMC_ENABLE 0x00080000
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#define SCOM_RAMC_THREADSEL 0x00060000
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#define SCOM_RAMC_EXECUTE 0x00010000
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#define SCOM_RAMC_MSR_OVERRIDE 0x00008000
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#define SCOM_RAMC_MSR_PR 0x00004000
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#define SCOM_RAMC_MSR_GS 0x00002000
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#define SCOM_RAMC_FORCE 0x00001000
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#define SCOM_RAMC_FLUSH 0x00000800
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#define SCOM_RAMC_INTERRUPT 0x00000004
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#define SCOM_RAMC_ERROR 0x00000002
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#define SCOM_RAMC_DONE 0x00000001
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#define SCOM_RAMI 0x29 /* Ram Instruction */
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#define SCOM_RAMIC 0x28 /* Ram Instruction and Command */
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#define SCOM_RAMIC_INSN 0xffffffff00000000
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#define SCOM_RAMD 0x2d /* Ram Data */
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#define SCOM_RAMDH 0x2e /* Ram Data High */
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#define SCOM_RAMDL 0x2f /* Ram Data Low */
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#define SCOM_PCCR0 0x33 /* PC Configuration Register 0 */
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#define SCOM_PCCR0_ENABLE_DEBUG 0x80000000
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#define SCOM_PCCR0_ENABLE_RAM 0x40000000
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#define SCOM_THRCTL 0x30 /* Thread Control and Status */
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#define SCOM_THRCTL_T0_STOP 0x80000000
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#define SCOM_THRCTL_T1_STOP 0x40000000
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#define SCOM_THRCTL_T2_STOP 0x20000000
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#define SCOM_THRCTL_T3_STOP 0x10000000
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#define SCOM_THRCTL_T0_STEP 0x08000000
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#define SCOM_THRCTL_T1_STEP 0x04000000
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#define SCOM_THRCTL_T2_STEP 0x02000000
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#define SCOM_THRCTL_T3_STEP 0x01000000
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#define SCOM_THRCTL_T0_RUN 0x00800000
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#define SCOM_THRCTL_T1_RUN 0x00400000
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#define SCOM_THRCTL_T2_RUN 0x00200000
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#define SCOM_THRCTL_T3_RUN 0x00100000
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#define SCOM_THRCTL_T0_PM 0x00080000
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#define SCOM_THRCTL_T1_PM 0x00040000
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#define SCOM_THRCTL_T2_PM 0x00020000
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#define SCOM_THRCTL_T3_PM 0x00010000
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#define SCOM_THRCTL_T0_UDE 0x00008000
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#define SCOM_THRCTL_T1_UDE 0x00004000
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#define SCOM_THRCTL_T2_UDE 0x00002000
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#define SCOM_THRCTL_T3_UDE 0x00001000
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#define SCOM_THRCTL_ASYNC_DIS 0x00000800
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#define SCOM_THRCTL_TB_DIS 0x00000400
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#define SCOM_THRCTL_DEC_DIS 0x00000200
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#define SCOM_THRCTL_AND 0x31 /* Thread Control and Status */
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#define SCOM_THRCTL_OR 0x32 /* Thread Control and Status */
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static DEFINE_PER_CPU(scom_map_t, scom_ptrs);
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static scom_map_t get_scom(int cpu, struct device_node *np, int *first_thread)
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{
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scom_map_t scom = per_cpu(scom_ptrs, cpu);
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int tcpu;
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if (scom_map_ok(scom)) {
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*first_thread = 0;
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return scom;
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}
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*first_thread = 1;
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scom = scom_map_device(np, 0);
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for (tcpu = cpu_first_thread_sibling(cpu);
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tcpu <= cpu_last_thread_sibling(cpu); tcpu++)
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per_cpu(scom_ptrs, tcpu) = scom;
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/* Hack: for the boot core, this will actually get called on
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* the second thread up, not the first so our test above will
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* set first_thread incorrectly. */
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if (cpu_first_thread_sibling(cpu) == 0)
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*first_thread = 0;
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return scom;
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}
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static int a2_scom_ram(scom_map_t scom, int thread, u32 insn, int extmask)
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{
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u64 cmd, mask, val;
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int n = 0;
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cmd = ((u64)insn << 32) | (((u64)extmask & 0xf) << 28)
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| ((u64)thread << 17) | SCOM_RAMC_ENABLE | SCOM_RAMC_EXECUTE;
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mask = SCOM_RAMC_DONE | SCOM_RAMC_INTERRUPT | SCOM_RAMC_ERROR;
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scom_write(scom, SCOM_RAMIC, cmd);
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for (;;) {
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if (scom_read(scom, SCOM_RAMC, &val) != 0) {
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pr_err("SCOM error on instruction 0x%08x, thread %d\n",
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insn, thread);
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return -1;
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}
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if (val & mask)
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break;
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pr_devel("Waiting on RAMC = 0x%llx\n", val);
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if (++n == 3) {
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pr_err("RAMC timeout on instruction 0x%08x, thread %d\n",
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insn, thread);
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return -1;
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}
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}
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if (val & SCOM_RAMC_INTERRUPT) {
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pr_err("RAMC interrupt on instruction 0x%08x, thread %d\n",
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insn, thread);
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return -SCOM_RAMC_INTERRUPT;
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}
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if (val & SCOM_RAMC_ERROR) {
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pr_err("RAMC error on instruction 0x%08x, thread %d\n",
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insn, thread);
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return -SCOM_RAMC_ERROR;
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}
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return 0;
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}
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static int a2_scom_getgpr(scom_map_t scom, int thread, int gpr, int alt,
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u64 *out_gpr)
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{
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int rc;
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/* or rN, rN, rN */
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u32 insn = 0x7c000378 | (gpr << 21) | (gpr << 16) | (gpr << 11);
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rc = a2_scom_ram(scom, thread, insn, alt ? 0xf : 0x0);
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if (rc)
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return rc;
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return scom_read(scom, SCOM_RAMD, out_gpr);
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}
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static int a2_scom_getspr(scom_map_t scom, int thread, int spr, u64 *out_spr)
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{
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int rc, sprhi, sprlo;
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u32 insn;
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sprhi = spr >> 5;
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sprlo = spr & 0x1f;
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insn = 0x7c2002a6 | (sprlo << 16) | (sprhi << 11); /* mfspr r1,spr */
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if (spr == 0x0ff0)
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insn = 0x7c2000a6; /* mfmsr r1 */
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rc = a2_scom_ram(scom, thread, insn, 0xf);
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if (rc)
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return rc;
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return a2_scom_getgpr(scom, thread, 1, 1, out_spr);
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}
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static int a2_scom_setgpr(scom_map_t scom, int thread, int gpr,
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int alt, u64 val)
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{
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u32 lis = 0x3c000000 | (gpr << 21);
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u32 li = 0x38000000 | (gpr << 21);
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u32 oris = 0x64000000 | (gpr << 21) | (gpr << 16);
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u32 ori = 0x60000000 | (gpr << 21) | (gpr << 16);
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u32 rldicr32 = 0x780007c6 | (gpr << 21) | (gpr << 16);
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u32 highest = val >> 48;
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u32 higher = (val >> 32) & 0xffff;
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u32 high = (val >> 16) & 0xffff;
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u32 low = val & 0xffff;
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int lext = alt ? 0x8 : 0x0;
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int oext = alt ? 0xf : 0x0;
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int rc = 0;
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if (highest)
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rc |= a2_scom_ram(scom, thread, lis | highest, lext);
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if (higher) {
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if (highest)
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rc |= a2_scom_ram(scom, thread, oris | higher, oext);
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else
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rc |= a2_scom_ram(scom, thread, li | higher, lext);
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}
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if (highest || higher)
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rc |= a2_scom_ram(scom, thread, rldicr32, oext);
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if (high) {
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if (highest || higher)
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rc |= a2_scom_ram(scom, thread, oris | high, oext);
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else
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rc |= a2_scom_ram(scom, thread, lis | high, lext);
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}
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if (highest || higher || high)
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rc |= a2_scom_ram(scom, thread, ori | low, oext);
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else
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rc |= a2_scom_ram(scom, thread, li | low, lext);
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return rc;
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}
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static int a2_scom_setspr(scom_map_t scom, int thread, int spr, u64 val)
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{
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int sprhi = spr >> 5;
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int sprlo = spr & 0x1f;
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/* mtspr spr, r1 */
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u32 insn = 0x7c2003a6 | (sprlo << 16) | (sprhi << 11);
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if (spr == 0x0ff0)
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insn = 0x7c200124; /* mtmsr r1 */
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if (a2_scom_setgpr(scom, thread, 1, 1, val))
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return -1;
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return a2_scom_ram(scom, thread, insn, 0xf);
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}
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static int a2_scom_initial_tlb(scom_map_t scom, int thread)
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{
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extern u32 a2_tlbinit_code_start[], a2_tlbinit_code_end[];
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extern u32 a2_tlbinit_after_iprot_flush[];
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extern u32 a2_tlbinit_after_linear_map[];
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u32 assoc, entries, i;
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u64 epn, tlbcfg;
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u32 *p;
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int rc;
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/* Invalidate all entries (including iprot) */
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rc = a2_scom_getspr(scom, thread, SPRN_TLB0CFG, &tlbcfg);
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if (rc)
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goto scom_fail;
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entries = tlbcfg & TLBnCFG_N_ENTRY;
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assoc = (tlbcfg & TLBnCFG_ASSOC) >> 24;
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epn = 0;
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/* Set MMUCR2 to enable 4K, 64K, 1M, 16M and 1G pages */
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a2_scom_setspr(scom, thread, SPRN_MMUCR2, 0x000a7531);
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/* Set MMUCR3 to write all thids bit to the TLB */
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a2_scom_setspr(scom, thread, SPRN_MMUCR3, 0x0000000f);
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/* Set MAS1 for 1G page size, and MAS2 to our initial EPN */
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a2_scom_setspr(scom, thread, SPRN_MAS1, MAS1_TSIZE(BOOK3E_PAGESZ_1GB));
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a2_scom_setspr(scom, thread, SPRN_MAS2, epn);
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for (i = 0; i < entries; i++) {
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a2_scom_setspr(scom, thread, SPRN_MAS0, MAS0_ESEL(i % assoc));
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/* tlbwe */
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rc = a2_scom_ram(scom, thread, 0x7c0007a4, 0);
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if (rc)
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goto scom_fail;
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/* Next entry is new address? */
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if((i + 1) % assoc == 0) {
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epn += (1 << 30);
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a2_scom_setspr(scom, thread, SPRN_MAS2, epn);
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}
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}
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/* Setup args for linear mapping */
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rc = a2_scom_setgpr(scom, thread, 3, 0, MAS0_TLBSEL(0));
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if (rc)
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goto scom_fail;
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/* Linear mapping */
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for (p = a2_tlbinit_code_start; p < a2_tlbinit_after_linear_map; p++) {
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rc = a2_scom_ram(scom, thread, *p, 0);
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if (rc)
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goto scom_fail;
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}
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/*
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* For the boot thread, between the linear mapping and the debug
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* mappings there is a loop to flush iprot mappings. Ramming doesn't do
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* branches, but the secondary threads don't need to be nearly as smart
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* (i.e. we don't need to worry about invalidating the mapping we're
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* standing on).
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*/
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/* Debug mappings. Expects r11 = MAS0 from linear map (set above) */
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for (p = a2_tlbinit_after_iprot_flush; p < a2_tlbinit_code_end; p++) {
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rc = a2_scom_ram(scom, thread, *p, 0);
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if (rc)
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goto scom_fail;
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}
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scom_fail:
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if (rc)
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pr_err("Setting up initial TLB failed, err %d\n", rc);
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if (rc == -SCOM_RAMC_INTERRUPT) {
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/* Interrupt, dump some status */
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int rc[10];
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u64 iar, srr0, srr1, esr, mas0, mas1, mas2, mas7_3, mas8, ccr2;
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rc[0] = a2_scom_getspr(scom, thread, SPRN_IAR, &iar);
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rc[1] = a2_scom_getspr(scom, thread, SPRN_SRR0, &srr0);
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rc[2] = a2_scom_getspr(scom, thread, SPRN_SRR1, &srr1);
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rc[3] = a2_scom_getspr(scom, thread, SPRN_ESR, &esr);
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rc[4] = a2_scom_getspr(scom, thread, SPRN_MAS0, &mas0);
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rc[5] = a2_scom_getspr(scom, thread, SPRN_MAS1, &mas1);
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rc[6] = a2_scom_getspr(scom, thread, SPRN_MAS2, &mas2);
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rc[7] = a2_scom_getspr(scom, thread, SPRN_MAS7_MAS3, &mas7_3);
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rc[8] = a2_scom_getspr(scom, thread, SPRN_MAS8, &mas8);
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rc[9] = a2_scom_getspr(scom, thread, SPRN_A2_CCR2, &ccr2);
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pr_err(" -> retreived IAR =0x%llx (err %d)\n", iar, rc[0]);
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pr_err(" retreived SRR0=0x%llx (err %d)\n", srr0, rc[1]);
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pr_err(" retreived SRR1=0x%llx (err %d)\n", srr1, rc[2]);
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pr_err(" retreived ESR =0x%llx (err %d)\n", esr, rc[3]);
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pr_err(" retreived MAS0=0x%llx (err %d)\n", mas0, rc[4]);
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pr_err(" retreived MAS1=0x%llx (err %d)\n", mas1, rc[5]);
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pr_err(" retreived MAS2=0x%llx (err %d)\n", mas2, rc[6]);
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pr_err(" retreived MS73=0x%llx (err %d)\n", mas7_3, rc[7]);
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pr_err(" retreived MAS8=0x%llx (err %d)\n", mas8, rc[8]);
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pr_err(" retreived CCR2=0x%llx (err %d)\n", ccr2, rc[9]);
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}
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return rc;
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}
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int a2_scom_startup_cpu(unsigned int lcpu, int thr_idx, struct device_node *np)
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{
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u64 init_iar, init_msr, init_ccr2;
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unsigned long start_here;
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int rc, core_setup;
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scom_map_t scom;
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u64 pccr0;
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scom = get_scom(lcpu, np, &core_setup);
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if (!scom) {
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printk(KERN_ERR "Couldn't map SCOM for CPU%d\n", lcpu);
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return -1;
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}
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pr_devel("Bringing up CPU%d using SCOM...\n", lcpu);
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if (scom_read(scom, SCOM_PCCR0, &pccr0) != 0) {
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printk(KERN_ERR "XSCOM failure readng PCCR0 on CPU%d\n", lcpu);
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return -1;
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}
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scom_write(scom, SCOM_PCCR0, pccr0 | SCOM_PCCR0_ENABLE_DEBUG |
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SCOM_PCCR0_ENABLE_RAM);
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/* Stop the thead with THRCTL. If we are setting up the TLB we stop all
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* threads. We also disable asynchronous interrupts while RAMing.
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*/
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if (core_setup)
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scom_write(scom, SCOM_THRCTL_OR,
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SCOM_THRCTL_T0_STOP |
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SCOM_THRCTL_T1_STOP |
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SCOM_THRCTL_T2_STOP |
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SCOM_THRCTL_T3_STOP |
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SCOM_THRCTL_ASYNC_DIS);
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else
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scom_write(scom, SCOM_THRCTL_OR, SCOM_THRCTL_T0_STOP >> thr_idx);
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/* Flush its pipeline just in case */
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scom_write(scom, SCOM_RAMC, ((u64)thr_idx << 17) |
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SCOM_RAMC_FLUSH | SCOM_RAMC_ENABLE);
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a2_scom_getspr(scom, thr_idx, SPRN_IAR, &init_iar);
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a2_scom_getspr(scom, thr_idx, 0x0ff0, &init_msr);
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a2_scom_getspr(scom, thr_idx, SPRN_A2_CCR2, &init_ccr2);
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/* Set MSR to MSR_CM (0x0ff0 is magic value for MSR_CM) */
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rc = a2_scom_setspr(scom, thr_idx, 0x0ff0, MSR_CM);
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if (rc) {
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pr_err("Failed to set MSR ! err %d\n", rc);
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return rc;
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}
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/* RAM in an sync/isync for the sake of it */
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a2_scom_ram(scom, thr_idx, 0x7c0004ac, 0);
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a2_scom_ram(scom, thr_idx, 0x4c00012c, 0);
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if (core_setup) {
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pr_devel("CPU%d is first thread in core, initializing TLB...\n",
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lcpu);
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rc = a2_scom_initial_tlb(scom, thr_idx);
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if (rc)
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goto fail;
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}
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start_here = *(unsigned long *)(core_setup ? generic_secondary_smp_init
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: generic_secondary_thread_init);
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pr_devel("CPU%d entry point at 0x%lx...\n", lcpu, start_here);
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rc |= a2_scom_setspr(scom, thr_idx, SPRN_IAR, start_here);
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rc |= a2_scom_setgpr(scom, thr_idx, 3, 0,
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get_hard_smp_processor_id(lcpu));
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/*
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* Tell book3e_secondary_core_init not to set up the TLB, we've
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* already done that.
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*/
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rc |= a2_scom_setgpr(scom, thr_idx, 4, 0, 1);
|
|
|
|
rc |= a2_scom_setspr(scom, thr_idx, SPRN_TENS, 0x1 << thr_idx);
|
|
|
|
scom_write(scom, SCOM_RAMC, 0);
|
|
scom_write(scom, SCOM_THRCTL_AND, ~(SCOM_THRCTL_T0_STOP >> thr_idx));
|
|
scom_write(scom, SCOM_PCCR0, pccr0);
|
|
fail:
|
|
pr_devel(" SCOM initialization %s\n", rc ? "failed" : "succeeded");
|
|
if (rc) {
|
|
pr_err("Old IAR=0x%08llx MSR=0x%08llx CCR2=0x%08llx\n",
|
|
init_iar, init_msr, init_ccr2);
|
|
}
|
|
|
|
return rc;
|
|
}
|