161 lines
3.9 KiB
C
161 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* Ingenic XBurst platform IRQ support
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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struct ingenic_intc_data {
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void __iomem *base;
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struct irq_domain *domain;
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unsigned num_chips;
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};
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#define JZ_REG_INTC_STATUS 0x00
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#define JZ_REG_INTC_MASK 0x04
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#define JZ_REG_INTC_SET_MASK 0x08
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#define JZ_REG_INTC_CLEAR_MASK 0x0c
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#define JZ_REG_INTC_PENDING 0x10
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#define CHIP_SIZE 0x20
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static irqreturn_t intc_cascade(int irq, void *data)
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{
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struct ingenic_intc_data *intc = irq_get_handler_data(irq);
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struct irq_domain *domain = intc->domain;
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struct irq_chip_generic *gc;
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uint32_t pending;
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unsigned i;
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for (i = 0; i < intc->num_chips; i++) {
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gc = irq_get_domain_generic_chip(domain, i * 32);
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pending = irq_reg_readl(gc, JZ_REG_INTC_PENDING);
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if (!pending)
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continue;
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while (pending) {
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int bit = __fls(pending);
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irq = irq_linear_revmap(domain, bit + (i * 32));
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generic_handle_irq(irq);
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pending &= ~BIT(bit);
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}
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}
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return IRQ_HANDLED;
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}
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static int __init ingenic_intc_of_init(struct device_node *node,
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unsigned num_chips)
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{
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struct ingenic_intc_data *intc;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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struct irq_domain *domain;
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int parent_irq, err = 0;
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unsigned i;
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intc = kzalloc(sizeof(*intc), GFP_KERNEL);
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if (!intc) {
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err = -ENOMEM;
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goto out_err;
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}
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parent_irq = irq_of_parse_and_map(node, 0);
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if (!parent_irq) {
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err = -EINVAL;
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goto out_free;
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}
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err = irq_set_handler_data(parent_irq, intc);
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if (err)
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goto out_unmap_irq;
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intc->num_chips = num_chips;
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intc->base = of_iomap(node, 0);
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if (!intc->base) {
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err = -ENODEV;
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goto out_unmap_irq;
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}
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domain = irq_domain_add_linear(node, num_chips * 32,
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&irq_generic_chip_ops, NULL);
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if (!domain) {
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err = -ENOMEM;
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goto out_unmap_base;
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}
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intc->domain = domain;
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err = irq_alloc_domain_generic_chips(domain, 32, 1, "INTC",
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handle_level_irq, 0,
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IRQ_NOPROBE | IRQ_LEVEL, 0);
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if (err)
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goto out_domain_remove;
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for (i = 0; i < num_chips; i++) {
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gc = irq_get_domain_generic_chip(domain, i * 32);
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gc->wake_enabled = IRQ_MSK(32);
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gc->reg_base = intc->base + (i * CHIP_SIZE);
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ct = gc->chip_types;
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ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
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ct->regs.disable = JZ_REG_INTC_SET_MASK;
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
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/* Mask all irqs */
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irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);
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}
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if (request_irq(parent_irq, intc_cascade, IRQF_NO_SUSPEND,
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"SoC intc cascade interrupt", NULL))
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pr_err("Failed to register SoC intc cascade interrupt\n");
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return 0;
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out_domain_remove:
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irq_domain_remove(domain);
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out_unmap_base:
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iounmap(intc->base);
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out_unmap_irq:
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irq_dispose_mapping(parent_irq);
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out_free:
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kfree(intc);
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out_err:
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return err;
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}
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static int __init intc_1chip_of_init(struct device_node *node,
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struct device_node *parent)
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{
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return ingenic_intc_of_init(node, 1);
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}
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IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init);
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IRQCHIP_DECLARE(jz4725b_intc, "ingenic,jz4725b-intc", intc_1chip_of_init);
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static int __init intc_2chip_of_init(struct device_node *node,
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struct device_node *parent)
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{
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return ingenic_intc_of_init(node, 2);
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}
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IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
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IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
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IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
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