167 lines
4.8 KiB
C
167 lines
4.8 KiB
C
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Authors: Rusty Russell <rusty@rustcorp.au>
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* Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/kvm_host.h>
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#include <asm/cputype.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_coproc.h>
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#include <linux/init.h>
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static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
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{
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/*
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* Compute guest MPIDR:
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* (Even if we present only one VCPU to the guest on an SMP
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* host we don't set the U bit in the MPIDR, or vice versa, as
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* revealing the underlying hardware properties is likely to
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* be the best choice).
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*/
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vcpu->arch.cp15[c0_MPIDR] = (read_cpuid_mpidr() & ~MPIDR_LEVEL_MASK)
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| (vcpu->vcpu_id & MPIDR_LEVEL_MASK);
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}
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#include "coproc.h"
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/* A15 TRM 4.3.28: RO WI */
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static bool access_actlr(struct kvm_vcpu *vcpu,
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const struct coproc_params *p,
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const struct coproc_reg *r)
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{
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if (p->is_write)
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return ignore_write(vcpu, p);
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*vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c1_ACTLR];
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return true;
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}
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/* A15 TRM 4.3.60: R/O. */
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static bool access_cbar(struct kvm_vcpu *vcpu,
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const struct coproc_params *p,
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const struct coproc_reg *r)
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{
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if (p->is_write)
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return write_to_read_only(vcpu, p);
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return read_zero(vcpu, p);
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}
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/* A15 TRM 4.3.48: R/O WI. */
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static bool access_l2ctlr(struct kvm_vcpu *vcpu,
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const struct coproc_params *p,
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const struct coproc_reg *r)
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{
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if (p->is_write)
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return ignore_write(vcpu, p);
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*vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[c9_L2CTLR];
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return true;
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}
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static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
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{
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u32 l2ctlr, ncores;
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asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
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l2ctlr &= ~(3 << 24);
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ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1;
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l2ctlr |= (ncores & 3) << 24;
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vcpu->arch.cp15[c9_L2CTLR] = l2ctlr;
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}
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static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
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{
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u32 actlr;
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/* ACTLR contains SMP bit: make sure you create all cpus first! */
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asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
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/* Make the SMP bit consistent with the guest configuration */
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if (atomic_read(&vcpu->kvm->online_vcpus) > 1)
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actlr |= 1U << 6;
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else
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actlr &= ~(1U << 6);
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vcpu->arch.cp15[c1_ACTLR] = actlr;
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}
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/* A15 TRM 4.3.49: R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored). */
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static bool access_l2ectlr(struct kvm_vcpu *vcpu,
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const struct coproc_params *p,
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const struct coproc_reg *r)
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{
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if (p->is_write)
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return ignore_write(vcpu, p);
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*vcpu_reg(vcpu, p->Rt1) = 0;
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return true;
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}
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/*
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* A15-specific CP15 registers.
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* CRn denotes the primary register number, but is copied to the CRm in the
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* user space API for 64-bit register access in line with the terminology used
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* in the ARM ARM.
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* Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
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* registers preceding 32-bit ones.
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*/
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static const struct coproc_reg a15_regs[] = {
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/* MPIDR: we use VMPIDR for guest access. */
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{ CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
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NULL, reset_mpidr, c0_MPIDR },
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/* SCTLR: swapped by interrupt.S. */
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{ CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
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NULL, reset_val, c1_SCTLR, 0x00C50078 },
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/* ACTLR: trapped by HCR.TAC bit. */
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{ CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
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access_actlr, reset_actlr, c1_ACTLR },
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/* CPACR: swapped by interrupt.S. */
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{ CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
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NULL, reset_val, c1_CPACR, 0x00000000 },
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/*
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* L2CTLR access (guest wants to know #CPUs).
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*/
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{ CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32,
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access_l2ctlr, reset_l2ctlr, c9_L2CTLR },
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{ CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr},
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/* The Configuration Base Address Register. */
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{ CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar},
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};
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static struct kvm_coproc_target_table a15_target_table = {
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.target = KVM_ARM_TARGET_CORTEX_A15,
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.table = a15_regs,
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.num = ARRAY_SIZE(a15_regs),
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};
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static int __init coproc_a15_init(void)
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{
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unsigned int i;
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for (i = 1; i < ARRAY_SIZE(a15_regs); i++)
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BUG_ON(cmp_reg(&a15_regs[i-1],
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&a15_regs[i]) >= 0);
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kvm_register_target_coproc_table(&a15_target_table);
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return 0;
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}
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late_initcall(coproc_a15_init);
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