403 lines
9.8 KiB
C
403 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_wakeirq.h>
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#include <linux/rtc.h>
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#define SNVS_LPREGISTER_OFFSET 0x34
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/* These register offsets are relative to LP (Low Power) range */
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#define SNVS_LPCR 0x04
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#define SNVS_LPSR 0x18
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#define SNVS_LPSRTCMR 0x1c
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#define SNVS_LPSRTCLR 0x20
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#define SNVS_LPTAR 0x24
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#define SNVS_LPPGDR 0x30
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#define SNVS_LPCR_SRTC_ENV (1 << 0)
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#define SNVS_LPCR_LPTA_EN (1 << 1)
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#define SNVS_LPCR_LPWUI_EN (1 << 3)
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#define SNVS_LPSR_LPTA (1 << 0)
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#define SNVS_LPPGDR_INIT 0x41736166
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#define CNTR_TO_SECS_SH 15
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struct snvs_rtc_data {
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struct rtc_device *rtc;
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struct regmap *regmap;
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int offset;
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int irq;
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struct clk *clk;
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};
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/* Read 64 bit timer register, which could be in inconsistent state */
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static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
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{
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u32 msb, lsb;
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regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
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regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
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return (u64)msb << 32 | lsb;
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}
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/* Read the secure real time counter, taking care to deal with the cases of the
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* counter updating while being read.
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*/
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static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
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{
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u64 read1, read2;
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unsigned int timeout = 100;
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/* As expected, the registers might update between the read of the LSB
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* reg and the MSB reg. It's also possible that one register might be
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* in partially modified state as well.
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*/
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read1 = rtc_read_lpsrt(data);
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do {
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read2 = read1;
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read1 = rtc_read_lpsrt(data);
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} while (read1 != read2 && --timeout);
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if (!timeout)
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dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
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/* Convert 47-bit counter to 32-bit raw second count */
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return (u32) (read1 >> CNTR_TO_SECS_SH);
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}
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/* Just read the lsb from the counter, dealing with inconsistent state */
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static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
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{
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u32 count1, count2;
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unsigned int timeout = 100;
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regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
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do {
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count2 = count1;
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regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
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} while (count1 != count2 && --timeout);
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if (!timeout) {
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dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
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return -ETIMEDOUT;
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}
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*lsb = count1;
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return 0;
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}
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static int rtc_write_sync_lp(struct snvs_rtc_data *data)
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{
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u32 count1, count2;
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u32 elapsed;
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unsigned int timeout = 1000;
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int ret;
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ret = rtc_read_lp_counter_lsb(data, &count1);
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if (ret)
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return ret;
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/* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
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do {
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ret = rtc_read_lp_counter_lsb(data, &count2);
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if (ret)
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return ret;
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elapsed = count2 - count1; /* wrap around _is_ handled! */
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} while (elapsed < 3 && --timeout);
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if (!timeout) {
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dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
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{
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int timeout = 1000;
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u32 lpcr;
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regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
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enable ? SNVS_LPCR_SRTC_ENV : 0);
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while (--timeout) {
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regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
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if (enable) {
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if (lpcr & SNVS_LPCR_SRTC_ENV)
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break;
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} else {
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if (!(lpcr & SNVS_LPCR_SRTC_ENV))
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break;
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}
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}
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if (!timeout)
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return -ETIMEDOUT;
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return 0;
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}
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static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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unsigned long time = rtc_read_lp_counter(data);
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rtc_time64_to_tm(time, tm);
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return 0;
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}
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static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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unsigned long time = rtc_tm_to_time64(tm);
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int ret;
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/* Disable RTC first */
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ret = snvs_rtc_enable(data, false);
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if (ret)
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return ret;
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/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
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regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
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regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
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/* Enable RTC again */
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ret = snvs_rtc_enable(data, true);
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return ret;
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}
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static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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u32 lptar, lpsr;
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regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
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rtc_time64_to_tm(lptar, &alrm->time);
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regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
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alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
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return 0;
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}
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static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
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(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
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enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
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return rtc_write_sync_lp(data);
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}
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static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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unsigned long time = rtc_tm_to_time64(&alrm->time);
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int ret;
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regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
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ret = rtc_write_sync_lp(data);
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if (ret)
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return ret;
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regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
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/* Clear alarm interrupt status bit */
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regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
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return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
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}
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static const struct rtc_class_ops snvs_rtc_ops = {
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.read_time = snvs_rtc_read_time,
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.set_time = snvs_rtc_set_time,
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.read_alarm = snvs_rtc_read_alarm,
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.set_alarm = snvs_rtc_set_alarm,
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.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
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};
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static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
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{
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struct device *dev = dev_id;
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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u32 lpsr;
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u32 events = 0;
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if (data->clk)
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clk_enable(data->clk);
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regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
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if (lpsr & SNVS_LPSR_LPTA) {
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events |= (RTC_AF | RTC_IRQF);
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/* RTC alarm should be one-shot */
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snvs_rtc_alarm_irq_enable(dev, 0);
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rtc_update_irq(data->rtc, 1, events);
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}
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/* clear interrupt status */
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regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
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if (data->clk)
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clk_disable(data->clk);
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return events ? IRQ_HANDLED : IRQ_NONE;
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}
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static const struct regmap_config snvs_rtc_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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static void snvs_rtc_action(void *data)
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{
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if (data)
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clk_disable_unprepare(data);
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}
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static int snvs_rtc_probe(struct platform_device *pdev)
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{
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struct snvs_rtc_data *data;
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int ret;
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void __iomem *mmio;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->rtc = devm_rtc_allocate_device(&pdev->dev);
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if (IS_ERR(data->rtc))
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return PTR_ERR(data->rtc);
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data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
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if (IS_ERR(data->regmap)) {
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dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
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mmio = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mmio))
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return PTR_ERR(mmio);
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data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
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} else {
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data->offset = SNVS_LPREGISTER_OFFSET;
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of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
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}
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if (IS_ERR(data->regmap)) {
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dev_err(&pdev->dev, "Can't find snvs syscon\n");
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return -ENODEV;
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}
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data->irq = platform_get_irq(pdev, 0);
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if (data->irq < 0)
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return data->irq;
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data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
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if (IS_ERR(data->clk)) {
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data->clk = NULL;
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} else {
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ret = clk_prepare_enable(data->clk);
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if (ret) {
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dev_err(&pdev->dev,
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"Could not prepare or enable the snvs clock\n");
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return ret;
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}
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}
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ret = devm_add_action_or_reset(&pdev->dev, snvs_rtc_action, data->clk);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, data);
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/* Initialize glitch detect */
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regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
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/* Clear interrupt status */
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regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
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/* Enable RTC */
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ret = snvs_rtc_enable(data, true);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
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return ret;
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}
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device_init_wakeup(&pdev->dev, true);
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ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
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if (ret)
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dev_err(&pdev->dev, "failed to enable irq wake\n");
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ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
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IRQF_SHARED, "rtc alarm", &pdev->dev);
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if (ret) {
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dev_err(&pdev->dev, "failed to request irq %d: %d\n",
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data->irq, ret);
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return ret;
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}
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data->rtc->ops = &snvs_rtc_ops;
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data->rtc->range_max = U32_MAX;
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return rtc_register_device(data->rtc);
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}
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static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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if (data->clk)
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clk_disable_unprepare(data->clk);
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return 0;
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}
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static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
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{
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struct snvs_rtc_data *data = dev_get_drvdata(dev);
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if (data->clk)
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return clk_prepare_enable(data->clk);
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return 0;
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}
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static const struct dev_pm_ops snvs_rtc_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
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};
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static const struct of_device_id snvs_dt_ids[] = {
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{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, snvs_dt_ids);
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static struct platform_driver snvs_rtc_driver = {
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.driver = {
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.name = "snvs_rtc",
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.pm = &snvs_rtc_pm_ops,
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.of_match_table = snvs_dt_ids,
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},
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.probe = snvs_rtc_probe,
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};
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module_platform_driver(snvs_rtc_driver);
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MODULE_AUTHOR("Freescale Semiconductor, Inc.");
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MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
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MODULE_LICENSE("GPL");
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