43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqchip/mips-gic.h>
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#include <linux/io.h>
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#include <asm/irq_cpu.h>
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#include <asm/setup.h>
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#include <asm/mips-boards/sead3int.h>
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#define SEAD_CONFIG_GIC_PRESENT_SHF 1
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#define SEAD_CONFIG_GIC_PRESENT_MSK (1 << SEAD_CONFIG_GIC_PRESENT_SHF)
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#define SEAD_CONFIG_BASE 0x1b100110
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#define SEAD_CONFIG_SIZE 4
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static void __iomem *sead3_config_reg;
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void __init arch_init_irq(void)
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{
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if (!cpu_has_veic)
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mips_cpu_irq_init();
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sead3_config_reg = ioremap_nocache(SEAD_CONFIG_BASE, SEAD_CONFIG_SIZE);
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gic_present = (__raw_readl(sead3_config_reg) &
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SEAD_CONFIG_GIC_PRESENT_MSK) >>
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SEAD_CONFIG_GIC_PRESENT_SHF;
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pr_info("GIC: %spresent\n", (gic_present) ? "" : "not ");
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pr_info("EIC: %s\n",
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(current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off");
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if (gic_present)
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gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, CPU_INT_GIC,
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MIPS_GIC_IRQ_BASE);
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}
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