217 lines
6.6 KiB
C
217 lines
6.6 KiB
C
#ifndef _ASM_IA64_SPINLOCK_H
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#define _ASM_IA64_SPINLOCK_H
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/*
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* Copyright (C) 1998-2003 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
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*
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* This file is used for SMP configurations only.
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*/
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <asm/atomic.h>
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#include <asm/bitops.h>
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#include <asm/intrinsics.h>
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#include <asm/system.h>
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#define __raw_spin_lock_init(x) ((x)->lock = 0)
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#ifdef ASM_SUPPORTED
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/*
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* Try to get the lock. If we fail to get the lock, make a non-standard call to
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* ia64_spinlock_contention(). We do not use a normal call because that would force all
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* callers of __raw_spin_lock() to be non-leaf routines. Instead, ia64_spinlock_contention() is
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* carefully coded to touch only those registers that __raw_spin_lock() marks "clobbered".
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*/
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#define IA64_SPINLOCK_CLOBBERS "ar.ccv", "ar.pfs", "p14", "p15", "r27", "r28", "r29", "r30", "b6", "memory"
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static inline void
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__raw_spin_lock_flags (raw_spinlock_t *lock, unsigned long flags)
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{
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register volatile unsigned int *ptr asm ("r31") = &lock->lock;
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#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
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# ifdef CONFIG_ITANIUM
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/* don't use brl on Itanium... */
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asm volatile ("{\n\t"
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" mov ar.ccv = r0\n\t"
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" mov r28 = ip\n\t"
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" mov r30 = 1;;\n\t"
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"}\n\t"
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"cmpxchg4.acq r30 = [%1], r30, ar.ccv\n\t"
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"movl r29 = ia64_spinlock_contention_pre3_4;;\n\t"
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"cmp4.ne p14, p0 = r30, r0\n\t"
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"mov b6 = r29;;\n\t"
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"mov r27=%2\n\t"
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"(p14) br.cond.spnt.many b6"
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: "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
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# else
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asm volatile ("{\n\t"
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" mov ar.ccv = r0\n\t"
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" mov r28 = ip\n\t"
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" mov r30 = 1;;\n\t"
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"}\n\t"
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"cmpxchg4.acq r30 = [%1], r30, ar.ccv;;\n\t"
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"cmp4.ne p14, p0 = r30, r0\n\t"
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"mov r27=%2\n\t"
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"(p14) brl.cond.spnt.many ia64_spinlock_contention_pre3_4;;"
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: "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
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# endif /* CONFIG_MCKINLEY */
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#else
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# ifdef CONFIG_ITANIUM
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/* don't use brl on Itanium... */
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/* mis-declare, so we get the entry-point, not it's function descriptor: */
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asm volatile ("mov r30 = 1\n\t"
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"mov r27=%2\n\t"
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"mov ar.ccv = r0;;\n\t"
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"cmpxchg4.acq r30 = [%0], r30, ar.ccv\n\t"
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"movl r29 = ia64_spinlock_contention;;\n\t"
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"cmp4.ne p14, p0 = r30, r0\n\t"
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"mov b6 = r29;;\n\t"
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"(p14) br.call.spnt.many b6 = b6"
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: "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
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# else
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asm volatile ("mov r30 = 1\n\t"
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"mov r27=%2\n\t"
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"mov ar.ccv = r0;;\n\t"
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"cmpxchg4.acq r30 = [%0], r30, ar.ccv;;\n\t"
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"cmp4.ne p14, p0 = r30, r0\n\t"
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"(p14) brl.call.spnt.many b6=ia64_spinlock_contention;;"
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: "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
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# endif /* CONFIG_MCKINLEY */
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#endif
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}
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#define __raw_spin_lock(lock) __raw_spin_lock_flags(lock, 0)
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/* Unlock by doing an ordered store and releasing the cacheline with nta */
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static inline void __raw_spin_unlock(raw_spinlock_t *x) {
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barrier();
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asm volatile ("st4.rel.nta [%0] = r0\n\t" :: "r"(x));
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}
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#else /* !ASM_SUPPORTED */
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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# define __raw_spin_lock(x) \
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do { \
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__u32 *ia64_spinlock_ptr = (__u32 *) (x); \
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__u64 ia64_spinlock_val; \
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ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
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if (unlikely(ia64_spinlock_val)) { \
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do { \
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while (*ia64_spinlock_ptr) \
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ia64_barrier(); \
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ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
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} while (ia64_spinlock_val); \
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} \
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} while (0)
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#define __raw_spin_unlock(x) do { barrier(); ((raw_spinlock_t *) x)->lock = 0; } while (0)
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#endif /* !ASM_SUPPORTED */
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#define __raw_spin_is_locked(x) ((x)->lock != 0)
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#define __raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
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#define __raw_spin_unlock_wait(lock) \
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do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
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#define __raw_read_can_lock(rw) (*(volatile int *)(rw) >= 0)
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#define __raw_write_can_lock(rw) (*(volatile int *)(rw) == 0)
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#define __raw_read_lock(rw) \
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do { \
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raw_rwlock_t *__read_lock_ptr = (rw); \
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\
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while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) { \
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ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
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while (*(volatile int *)__read_lock_ptr < 0) \
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cpu_relax(); \
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} \
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} while (0)
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#define __raw_read_unlock(rw) \
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do { \
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raw_rwlock_t *__read_lock_ptr = (rw); \
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ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
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} while (0)
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#ifdef ASM_SUPPORTED
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#define __raw_write_lock(rw) \
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do { \
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__asm__ __volatile__ ( \
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"mov ar.ccv = r0\n" \
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"dep r29 = -1, r0, 31, 1;;\n" \
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"1:\n" \
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"ld4 r2 = [%0];;\n" \
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"cmp4.eq p0,p7 = r0,r2\n" \
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"(p7) br.cond.spnt.few 1b \n" \
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"cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n" \
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"cmp4.eq p0,p7 = r0, r2\n" \
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"(p7) br.cond.spnt.few 1b;;\n" \
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:: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory"); \
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} while(0)
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#define __raw_write_trylock(rw) \
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({ \
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register long result; \
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\
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__asm__ __volatile__ ( \
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"mov ar.ccv = r0\n" \
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"dep r29 = -1, r0, 31, 1;;\n" \
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"cmpxchg4.acq %0 = [%1], r29, ar.ccv\n" \
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: "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \
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(result == 0); \
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})
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static inline void __raw_write_unlock(raw_rwlock_t *x)
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{
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u8 *y = (u8 *)x;
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barrier();
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asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
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}
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#else /* !ASM_SUPPORTED */
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#define __raw_write_lock(l) \
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({ \
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__u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \
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__u32 *ia64_write_lock_ptr = (__u32 *) (l); \
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do { \
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while (*ia64_write_lock_ptr) \
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ia64_barrier(); \
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ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0); \
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} while (ia64_val); \
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})
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#define __raw_write_trylock(rw) \
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({ \
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__u64 ia64_val; \
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__u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1); \
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ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \
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(ia64_val == 0); \
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})
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static inline void __raw_write_unlock(raw_rwlock_t *x)
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{
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barrier();
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x->write_lock = 0;
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}
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#endif /* !ASM_SUPPORTED */
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static inline int __raw_read_trylock(raw_rwlock_t *x)
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{
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union {
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raw_rwlock_t lock;
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__u32 word;
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} old, new;
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old.lock = new.lock = *x;
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old.lock.write_lock = new.lock.write_lock = 0;
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++new.lock.read_counter;
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return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
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}
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#endif /* _ASM_IA64_SPINLOCK_H */
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