358 lines
6.4 KiB
Plaintext
358 lines
6.4 KiB
Plaintext
config BF542
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def_bool y
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depends on BF542_std || BF542M
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config BF544
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def_bool y
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depends on BF544_std || BF544M
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config BF547
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def_bool y
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depends on BF547_std || BF547M
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config BF548
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def_bool y
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depends on BF548_std || BF548M
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config BF549
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def_bool y
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depends on BF549_std || BF549M
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config BF54xM
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def_bool y
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depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
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config BF54x
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def_bool y
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depends on (BF542 || BF544 || BF547 || BF548 || BF549)
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if (BF54x)
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source "arch/blackfin/mach-bf548/boards/Kconfig"
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menu "BF548 Specific Configuration"
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config DEB_DMA_URGENT
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bool "DMA has priority over core for ext. accesses"
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depends on BF54x
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default y
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help
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Treat any DEB1, DEB2 and DEB3 request as Urgent
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config BF548_ATAPI_ALTERNATIVE_PORT
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bool "BF548 ATAPI alternative port via GPIO"
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help
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BF548 ATAPI data and address PINs can be routed through
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async address or GPIO port F and G. Select y to route it
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to GPIO.
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comment "Interrupt Priority Assignment"
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menu "Priority"
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config IRQ_PLL_WAKEUP
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int "IRQ_PLL_WAKEUP"
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default 7
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config IRQ_DMAC0_ERR
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int "IRQ_DMAC0_ERR"
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default 7
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config IRQ_EPPI0_ERR
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int "IRQ_EPPI0_ERR"
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default 7
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config IRQ_SPORT0_ERR
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int "IRQ_SPORT0_ERR"
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default 7
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config IRQ_SPORT1_ERR
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int "IRQ_SPORT1_ERR"
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default 7
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config IRQ_SPI0_ERR
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int "IRQ_SPI0_ERR"
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default 7
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config IRQ_UART0_ERR
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int "IRQ_UART0_ERR"
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default 7
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config IRQ_RTC
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int "IRQ_RTC"
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default 8
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config IRQ_EPPI0
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int "IRQ_EPPI0"
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default 8
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config IRQ_SPORT0_RX
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int "IRQ_SPORT0_RX"
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default 9
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config IRQ_SPORT0_TX
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int "IRQ_SPORT0_TX"
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default 9
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config IRQ_SPORT1_RX
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int "IRQ_SPORT1_RX"
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default 9
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config IRQ_SPORT1_TX
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int "IRQ_SPORT1_TX"
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default 9
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config IRQ_SPI0
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int "IRQ_SPI0"
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default 10
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config IRQ_UART0_RX
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int "IRQ_UART0_RX"
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default 10
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config IRQ_UART0_TX
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int "IRQ_UART0_TX"
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default 10
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config IRQ_TIMER8
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int "IRQ_TIMER8"
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default 11
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config IRQ_TIMER9
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int "IRQ_TIMER9"
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default 11
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config IRQ_TIMER10
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int "IRQ_TIMER10"
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default 11
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config IRQ_PINT0
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int "IRQ_PINT0"
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default 12
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config IRQ_PINT1
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int "IRQ_PINT0"
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default 12
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config IRQ_MDMAS0
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int "IRQ_MDMAS0"
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default 13
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config IRQ_MDMAS1
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int "IRQ_DMDMAS1"
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default 13
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config IRQ_WATCHDOG
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int "IRQ_WATCHDOG"
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default 13
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config IRQ_DMAC1_ERR
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int "IRQ_DMAC1_ERR"
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default 7
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config IRQ_SPORT2_ERR
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int "IRQ_SPORT2_ERR"
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default 7
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config IRQ_SPORT3_ERR
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int "IRQ_SPORT3_ERR"
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default 7
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config IRQ_MXVR_DATA
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int "IRQ MXVR Data"
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default 7
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config IRQ_SPI1_ERR
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int "IRQ_SPI1_ERR"
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default 7
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config IRQ_SPI2_ERR
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int "IRQ_SPI2_ERR"
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default 7
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config IRQ_UART1_ERR
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int "IRQ_UART1_ERR"
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default 7
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config IRQ_UART2_ERR
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int "IRQ_UART2_ERR"
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default 7
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config IRQ_CAN0_ERR
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int "IRQ_CAN0_ERR"
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default 7
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config IRQ_SPORT2_RX
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int "IRQ_SPORT2_RX"
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default 9
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config IRQ_SPORT2_TX
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int "IRQ_SPORT2_TX"
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default 9
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config IRQ_SPORT3_RX
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int "IRQ_SPORT3_RX"
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default 9
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config IRQ_SPORT3_TX
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int "IRQ_SPORT3_TX"
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default 9
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config IRQ_EPPI1
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int "IRQ_EPPI1"
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default 9
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config IRQ_EPPI2
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int "IRQ_EPPI2"
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default 9
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config IRQ_SPI1
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int "IRQ_SPI1"
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default 10
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config IRQ_SPI2
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int "IRQ_SPI2"
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default 10
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config IRQ_UART1_RX
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int "IRQ_UART1_RX"
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default 10
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config IRQ_UART1_TX
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int "IRQ_UART1_TX"
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default 10
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config IRQ_ATAPI_RX
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int "IRQ_ATAPI_RX"
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default 10
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config IRQ_ATAPI_TX
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int "IRQ_ATAPI_TX"
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default 10
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config IRQ_TWI0
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int "IRQ_TWI0"
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default 11
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config IRQ_TWI1
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int "IRQ_TWI1"
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default 11
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config IRQ_CAN0_RX
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int "IRQ_CAN_RX"
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default 11
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config IRQ_CAN0_TX
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int "IRQ_CAN_TX"
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default 11
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config IRQ_MDMAS2
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int "IRQ_MDMAS2"
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default 13
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config IRQ_MDMAS3
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int "IRQ_DMMAS3"
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default 13
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config IRQ_MXVR_ERR
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int "IRQ_MXVR_ERR"
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default 11
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config IRQ_MXVR_MSG
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int "IRQ_MXVR_MSG"
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default 11
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config IRQ_MXVR_PKT
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int "IRQ_MXVR_PKT"
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default 11
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config IRQ_EPPI1_ERR
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int "IRQ_EPPI1_ERR"
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default 7
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config IRQ_EPPI2_ERR
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int "IRQ_EPPI2_ERR"
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default 7
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config IRQ_UART3_ERR
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int "IRQ_UART3_ERR"
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default 7
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config IRQ_HOST_ERR
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int "IRQ_HOST_ERR"
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default 7
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config IRQ_PIXC_ERR
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int "IRQ_PIXC_ERR"
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default 7
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config IRQ_NFC_ERR
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int "IRQ_NFC_ERR"
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default 7
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config IRQ_ATAPI_ERR
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int "IRQ_ATAPI_ERR"
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default 7
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config IRQ_CAN1_ERR
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int "IRQ_CAN1_ERR"
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default 7
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config IRQ_HS_DMA_ERR
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int "IRQ Handshake DMA Status"
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default 7
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config IRQ_PIXC_IN0
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int "IRQ PIXC IN0"
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default 8
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config IRQ_PIXC_IN1
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int "IRQ PIXC IN1"
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default 8
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config IRQ_PIXC_OUT
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int "IRQ PIXC OUT"
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default 8
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config IRQ_SDH
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int "IRQ SDH"
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default 8
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config IRQ_CNT
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int "IRQ CNT"
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default 8
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config IRQ_KEY
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int "IRQ KEY"
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default 8
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config IRQ_CAN1_RX
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int "IRQ CAN1 RX"
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default 11
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config IRQ_CAN1_TX
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int "IRQ_CAN1_TX"
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default 11
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config IRQ_SDH_MASK0
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int "IRQ_SDH_MASK0"
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default 11
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config IRQ_SDH_MASK1
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int "IRQ_SDH_MASK1"
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default 11
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config IRQ_USB_INT0
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int "IRQ USB INT0"
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default 11
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config IRQ_USB_INT1
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int "IRQ USB INT1"
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default 11
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config IRQ_USB_INT2
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int "IRQ USB INT2"
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default 11
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config IRQ_USB_DMA
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int "IRQ USB DMA"
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default 11
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config IRQ_OTPSEC
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int "IRQ OPTSEC"
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default 11
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config IRQ_TIMER0
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int "IRQ_TIMER0"
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default 7 if TICKSOURCE_GPTMR0
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default 8
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config IRQ_TIMER1
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int "IRQ_TIMER1"
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default 11
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config IRQ_TIMER2
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int "IRQ_TIMER2"
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default 11
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config IRQ_TIMER3
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int "IRQ_TIMER3"
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default 11
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config IRQ_TIMER4
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int "IRQ_TIMER4"
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default 11
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config IRQ_TIMER5
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int "IRQ_TIMER5"
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default 11
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config IRQ_TIMER6
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int "IRQ_TIMER6"
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default 11
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config IRQ_TIMER7
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int "IRQ_TIMER7"
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default 11
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config IRQ_PINT2
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int "IRQ_PIN2"
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default 11
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config IRQ_PINT3
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int "IRQ_PIN3"
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default 11
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help
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Enter the priority numbers between 7-13 ONLY. Others are Reserved.
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This applies to all the above. It is not recommended to assign the
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highest priority number 7 to UART or any other device.
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endmenu
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comment "Pin Interrupt to Port Assignment"
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menu "Assignment"
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config PINTx_REASSIGN
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bool "Reprogram PINT Assignment"
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default y
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help
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The interrupt assignment registers controls the pin-to-interrupt
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assignment in a byte-wide manner. Each option allows you to select
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a set of pins (High/Low Byte) of an specific Port being mapped
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to one of the four PIN Interrupts IRQ_PINTx.
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You shouldn't change any of these unless you know exactly what you're doing.
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Please consult the Blackfin BF54x Processor Hardware Reference Manual.
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config PINT0_ASSIGN
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hex "PINT0_ASSIGN"
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depends on PINTx_REASSIGN
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default 0x00000101
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config PINT1_ASSIGN
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hex "PINT1_ASSIGN"
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depends on PINTx_REASSIGN
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default 0x01010000
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config PINT2_ASSIGN
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hex "PINT2_ASSIGN"
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depends on PINTx_REASSIGN
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default 0x07000101
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config PINT3_ASSIGN
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hex "PINT3_ASSIGN"
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depends on PINTx_REASSIGN
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default 0x02020303
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endmenu
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endmenu
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endif
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