168 lines
5.5 KiB
C
168 lines
5.5 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <linux/export.h>
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#include <asm/page.h>
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#include <asm/cacheflush.h>
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#include <arch/icache.h>
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#include <arch/spr_def.h>
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void __flush_icache_range(unsigned long start, unsigned long end)
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{
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invalidate_icache((const void *)start, end - start, PAGE_SIZE);
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}
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/* Force a load instruction to issue. */
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static inline void force_load(char *p)
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{
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*(volatile char *)p;
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}
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/*
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* Flush and invalidate a VA range that is homed remotely on a single
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* core (if "!hfh") or homed via hash-for-home (if "hfh"), waiting
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* until the memory controller holds the flushed values.
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*/
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void __attribute__((optimize("omit-frame-pointer")))
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finv_buffer_remote(void *buffer, size_t size, int hfh)
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{
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char *p, *base;
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size_t step_size, load_count;
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/*
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* On TILEPro the striping granularity is a fixed 8KB; on
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* TILE-Gx it is configurable, and we rely on the fact that
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* the hypervisor always configures maximum striping, so that
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* bits 9 and 10 of the PA are part of the stripe function, so
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* every 512 bytes we hit a striping boundary.
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*
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*/
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#ifdef __tilegx__
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const unsigned long STRIPE_WIDTH = 512;
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#else
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const unsigned long STRIPE_WIDTH = 8192;
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#endif
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#ifdef __tilegx__
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/*
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* On TILE-Gx, we must disable the dstream prefetcher before doing
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* a cache flush; otherwise, we could end up with data in the cache
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* that we don't want there. Note that normally we'd do an mf
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* after the SPR write to disabling the prefetcher, but we do one
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* below, before any further loads, so there's no need to do it
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* here.
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*/
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uint_reg_t old_dstream_pf = __insn_mfspr(SPR_DSTREAM_PF);
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__insn_mtspr(SPR_DSTREAM_PF, 0);
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#endif
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/*
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* Flush and invalidate the buffer out of the local L1/L2
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* and request the home cache to flush and invalidate as well.
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*/
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__finv_buffer(buffer, size);
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/*
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* Wait for the home cache to acknowledge that it has processed
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* all the flush-and-invalidate requests. This does not mean
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* that the flushed data has reached the memory controller yet,
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* but it does mean the home cache is processing the flushes.
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*/
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__insn_mf();
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/*
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* Issue a load to the last cache line, which can't complete
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* until all the previously-issued flushes to the same memory
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* controller have also completed. If we weren't striping
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* memory, that one load would be sufficient, but since we may
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* be, we also need to back up to the last load issued to
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* another memory controller, which would be the point where
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* we crossed a "striping" boundary (the granularity of striping
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* across memory controllers). Keep backing up and doing this
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* until we are before the beginning of the buffer, or have
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* hit all the controllers.
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*
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* If we are flushing a hash-for-home buffer, it's even worse.
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* Each line may be homed on a different tile, and each tile
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* may have up to four lines that are on different
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* controllers. So as we walk backwards, we have to touch
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* enough cache lines to satisfy these constraints. In
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* practice this ends up being close enough to "load from
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* every cache line on a full memory stripe on each
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* controller" that we simply do that, to simplify the logic.
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*
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* On TILE-Gx the hash-for-home function is much more complex,
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* with the upshot being we can't readily guarantee we have
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* hit both entries in the 128-entry AMT that were hit by any
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* load in the entire range, so we just re-load them all.
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* With larger buffers, we may want to consider using a hypervisor
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* trap to issue loads directly to each hash-for-home tile for
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* each controller (doing it from Linux would trash the TLB).
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*/
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if (hfh) {
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step_size = L2_CACHE_BYTES;
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#ifdef __tilegx__
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load_count = (size + L2_CACHE_BYTES - 1) / L2_CACHE_BYTES;
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#else
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load_count = (STRIPE_WIDTH / L2_CACHE_BYTES) *
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(1 << CHIP_LOG_NUM_MSHIMS());
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#endif
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} else {
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step_size = STRIPE_WIDTH;
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load_count = (1 << CHIP_LOG_NUM_MSHIMS());
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}
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/* Load the last byte of the buffer. */
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p = (char *)buffer + size - 1;
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force_load(p);
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/* Bump down to the end of the previous stripe or cache line. */
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p -= step_size;
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p = (char *)((unsigned long)p | (step_size - 1));
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/* Figure out how far back we need to go. */
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base = p - (step_size * (load_count - 2));
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if ((unsigned long)base < (unsigned long)buffer)
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base = buffer;
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/* Fire all the loads we need. */
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for (; p >= base; p -= step_size)
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force_load(p);
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/*
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* Repeat, but with finv's instead of loads, to get rid of the
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* data we just loaded into our own cache and the old home L3.
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* The finv's are guaranteed not to actually flush the data in
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* the buffer back to their home, since we just read it, so the
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* lines are clean in cache; we will only invalidate those lines.
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*/
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p = (char *)buffer + size - 1;
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__insn_finv(p);
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p -= step_size;
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p = (char *)((unsigned long)p | (step_size - 1));
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for (; p >= base; p -= step_size)
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__insn_finv(p);
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/* Wait for these finv's (and thus the first finvs) to be done. */
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__insn_mf();
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#ifdef __tilegx__
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/* Reenable the prefetcher. */
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__insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
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#endif
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}
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EXPORT_SYMBOL_GPL(finv_buffer_remote);
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