182 lines
3.9 KiB
ArmAsm
182 lines
3.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013 ARM Ltd.
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* Copyright (C) 2013 Linaro.
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*
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* This code is based on glibc cortex strings work originally authored by Linaro
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* be found @
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*
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* http://bazaar.launchpad.net/~linaro-toolchain-dev/cortex-strings/trunk/
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* files/head:/src/aarch64/
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*/
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/*
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* Copy a buffer from src to dest (alignment handled by the hardware)
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*
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* Parameters:
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* x0 - dest
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* x1 - src
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* x2 - n
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* Returns:
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* x0 - dest
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*/
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dstin .req x0
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src .req x1
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count .req x2
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tmp1 .req x3
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tmp1w .req w3
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tmp2 .req x4
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tmp2w .req w4
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dst .req x6
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A_l .req x7
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A_h .req x8
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B_l .req x9
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B_h .req x10
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C_l .req x11
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C_h .req x12
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D_l .req x13
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D_h .req x14
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mov dst, dstin
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cmp count, #16
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/*When memory length is less than 16, the accessed are not aligned.*/
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b.lo .Ltiny15
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neg tmp2, src
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ands tmp2, tmp2, #15/* Bytes to reach alignment. */
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b.eq .LSrcAligned
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sub count, count, tmp2
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/*
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* Copy the leading memory data from src to dst in an increasing
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* address order.By this way,the risk of overwriting the source
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* memory data is eliminated when the distance between src and
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* dst is less than 16. The memory accesses here are alignment.
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*/
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tbz tmp2, #0, 1f
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ldrb1 tmp1w, src, #1
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strb1 tmp1w, dst, #1
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1:
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tbz tmp2, #1, 2f
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ldrh1 tmp1w, src, #2
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strh1 tmp1w, dst, #2
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2:
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tbz tmp2, #2, 3f
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ldr1 tmp1w, src, #4
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str1 tmp1w, dst, #4
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3:
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tbz tmp2, #3, .LSrcAligned
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ldr1 tmp1, src, #8
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str1 tmp1, dst, #8
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.LSrcAligned:
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cmp count, #64
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b.ge .Lcpy_over64
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/*
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* Deal with small copies quickly by dropping straight into the
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* exit block.
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*/
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.Ltail63:
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/*
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* Copy up to 48 bytes of data. At this point we only need the
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* bottom 6 bits of count to be accurate.
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*/
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ands tmp1, count, #0x30
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b.eq .Ltiny15
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cmp tmp1w, #0x20
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b.eq 1f
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b.lt 2f
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ldp1 A_l, A_h, src, #16
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stp1 A_l, A_h, dst, #16
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1:
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ldp1 A_l, A_h, src, #16
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stp1 A_l, A_h, dst, #16
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2:
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ldp1 A_l, A_h, src, #16
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stp1 A_l, A_h, dst, #16
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.Ltiny15:
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/*
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* Prefer to break one ldp/stp into several load/store to access
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* memory in an increasing address order,rather than to load/store 16
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* bytes from (src-16) to (dst-16) and to backward the src to aligned
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* address,which way is used in original cortex memcpy. If keeping
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* the original memcpy process here, memmove need to satisfy the
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* precondition that src address is at least 16 bytes bigger than dst
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* address,otherwise some source data will be overwritten when memove
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* call memcpy directly. To make memmove simpler and decouple the
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* memcpy's dependency on memmove, withdrew the original process.
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*/
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tbz count, #3, 1f
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ldr1 tmp1, src, #8
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str1 tmp1, dst, #8
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1:
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tbz count, #2, 2f
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ldr1 tmp1w, src, #4
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str1 tmp1w, dst, #4
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2:
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tbz count, #1, 3f
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ldrh1 tmp1w, src, #2
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strh1 tmp1w, dst, #2
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3:
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tbz count, #0, .Lexitfunc
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ldrb1 tmp1w, src, #1
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strb1 tmp1w, dst, #1
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b .Lexitfunc
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.Lcpy_over64:
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subs count, count, #128
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b.ge .Lcpy_body_large
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/*
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* Less than 128 bytes to copy, so handle 64 here and then jump
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* to the tail.
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*/
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ldp1 A_l, A_h, src, #16
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stp1 A_l, A_h, dst, #16
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ldp1 B_l, B_h, src, #16
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ldp1 C_l, C_h, src, #16
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stp1 B_l, B_h, dst, #16
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stp1 C_l, C_h, dst, #16
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ldp1 D_l, D_h, src, #16
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stp1 D_l, D_h, dst, #16
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tst count, #0x3f
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b.ne .Ltail63
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b .Lexitfunc
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/*
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* Critical loop. Start at a new cache line boundary. Assuming
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* 64 bytes per line this ensures the entire loop is in one line.
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*/
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.p2align L1_CACHE_SHIFT
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.Lcpy_body_large:
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/* pre-get 64 bytes data. */
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ldp1 A_l, A_h, src, #16
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ldp1 B_l, B_h, src, #16
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ldp1 C_l, C_h, src, #16
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ldp1 D_l, D_h, src, #16
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1:
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/*
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* interlace the load of next 64 bytes data block with store of the last
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* loaded 64 bytes data.
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*/
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stp1 A_l, A_h, dst, #16
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ldp1 A_l, A_h, src, #16
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stp1 B_l, B_h, dst, #16
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ldp1 B_l, B_h, src, #16
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stp1 C_l, C_h, dst, #16
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ldp1 C_l, C_h, src, #16
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stp1 D_l, D_h, dst, #16
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ldp1 D_l, D_h, src, #16
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subs count, count, #64
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b.ge 1b
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stp1 A_l, A_h, dst, #16
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stp1 B_l, B_h, dst, #16
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stp1 C_l, C_h, dst, #16
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stp1 D_l, D_h, dst, #16
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tst count, #0x3f
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b.ne .Ltail63
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.Lexitfunc:
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