169 lines
5.8 KiB
C
169 lines
5.8 KiB
C
/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Contact Information:
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qat-linux@intel.com
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BSD LICENSE
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Copyright(c) 2014 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "adf_accel_devices.h"
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#include "adf_transport_internal.h"
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#define ADF_ARB_NUM 4
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#define ADF_ARB_REQ_RING_NUM 8
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#define ADF_ARB_REG_SIZE 0x4
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#define ADF_ARB_WTR_SIZE 0x20
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#define ADF_ARB_OFFSET 0x30000
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#define ADF_ARB_REG_SLOT 0x1000
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#define ADF_ARB_WTR_OFFSET 0x010
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#define ADF_ARB_RO_EN_OFFSET 0x090
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#define ADF_ARB_WQCFG_OFFSET 0x100
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#define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
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#define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
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#define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
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ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
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(ADF_ARB_REG_SLOT * index), value)
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#define WRITE_CSR_ARB_RESPORDERING(csr_addr, index, value) \
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ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
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ADF_ARB_RO_EN_OFFSET) + (ADF_ARB_REG_SIZE * index), value)
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#define WRITE_CSR_ARB_WEIGHT(csr_addr, arb, index, value) \
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ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
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ADF_ARB_WTR_OFFSET) + (ADF_ARB_WTR_SIZE * arb) + \
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(ADF_ARB_REG_SIZE * index), value)
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#define WRITE_CSR_ARB_SARCONFIG(csr_addr, index, value) \
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ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \
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(ADF_ARB_REG_SIZE * index), value)
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#define WRITE_CSR_ARB_WRK_2_SER_MAP(csr_addr, index, value) \
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ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
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ADF_ARB_WRK_2_SER_MAP_OFFSET) + \
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(ADF_ARB_REG_SIZE * index), value)
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#define WRITE_CSR_ARB_WQCFG(csr_addr, index, value) \
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ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
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ADF_ARB_WQCFG_OFFSET) + (ADF_ARB_REG_SIZE * index), value)
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int adf_init_arb(struct adf_accel_dev *accel_dev)
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{
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
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u32 arb_cfg = 0x1 << 31 | 0x4 << 4 | 0x1;
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u32 arb, i;
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const u32 *thd_2_arb_cfg;
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/* Service arb configured for 32 bytes responses and
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* ring flow control check enabled. */
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for (arb = 0; arb < ADF_ARB_NUM; arb++)
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WRITE_CSR_ARB_SARCONFIG(csr, arb, arb_cfg);
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/* Setup service weighting */
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for (arb = 0; arb < ADF_ARB_NUM; arb++)
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for (i = 0; i < ADF_ARB_REQ_RING_NUM; i++)
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WRITE_CSR_ARB_WEIGHT(csr, arb, i, 0xFFFFFFFF);
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/* Setup ring response ordering */
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for (i = 0; i < ADF_ARB_REQ_RING_NUM; i++)
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WRITE_CSR_ARB_RESPORDERING(csr, i, 0xFFFFFFFF);
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/* Setup worker queue registers */
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for (i = 0; i < hw_data->num_engines; i++)
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WRITE_CSR_ARB_WQCFG(csr, i, i);
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/* Map worker threads to service arbiters */
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hw_data->get_arb_mapping(accel_dev, &thd_2_arb_cfg);
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if (!thd_2_arb_cfg)
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return -EFAULT;
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for (i = 0; i < hw_data->num_engines; i++)
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WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, *(thd_2_arb_cfg + i));
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return 0;
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}
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EXPORT_SYMBOL_GPL(adf_init_arb);
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/**
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* adf_update_ring_arb() - update ring arbitration rgister
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* @accel_dev: Pointer to ring data.
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*
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* Function enables or disables rings for/from arbitration.
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*/
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void adf_update_ring_arb(struct adf_etr_ring_data *ring)
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{
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WRITE_CSR_ARB_RINGSRVARBEN(ring->bank->csr_addr,
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ring->bank->bank_number,
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ring->bank->ring_mask & 0xFF);
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}
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EXPORT_SYMBOL_GPL(adf_update_ring_arb);
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void adf_exit_arb(struct adf_accel_dev *accel_dev)
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{
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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void __iomem *csr;
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unsigned int i;
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if (!accel_dev->transport)
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return;
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csr = accel_dev->transport->banks[0].csr_addr;
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/* Reset arbiter configuration */
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for (i = 0; i < ADF_ARB_NUM; i++)
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WRITE_CSR_ARB_SARCONFIG(csr, i, 0);
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/* Shutdown work queue */
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for (i = 0; i < hw_data->num_engines; i++)
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WRITE_CSR_ARB_WQCFG(csr, i, 0);
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/* Unmap worker threads to service arbiters */
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for (i = 0; i < hw_data->num_engines; i++)
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WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, 0);
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/* Disable arbitration on all rings */
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for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)
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WRITE_CSR_ARB_RINGSRVARBEN(csr, i, 0);
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}
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EXPORT_SYMBOL_GPL(adf_exit_arb);
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