336 lines
8.0 KiB
C
336 lines
8.0 KiB
C
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <asm/cacheflush.h>
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#include <asm/gic.h>
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#include <asm/mips-cm.h>
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#include <asm/mips-cpc.h>
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#include <asm/mips_mt.h>
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#include <asm/mipsregs.h>
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#include <asm/smp-cps.h>
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#include <asm/time.h>
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#include <asm/uasm.h>
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static DECLARE_BITMAP(core_power, NR_CPUS);
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struct boot_config mips_cps_bootcfg;
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static void init_core(void)
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{
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unsigned int nvpes, t;
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u32 mvpconf0, vpeconf0, vpecontrol, tcstatus, tcbind, status;
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if (!cpu_has_mipsmt)
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return;
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/* Enter VPE configuration state */
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dvpe();
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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/* Retrieve the count of VPEs in this core */
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mvpconf0 = read_c0_mvpconf0();
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nvpes = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
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smp_num_siblings = nvpes;
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for (t = 1; t < nvpes; t++) {
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/* Use a 1:1 mapping of TC index to VPE index */
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settc(t);
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/* Bind 1 TC to this VPE */
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tcbind = read_tc_c0_tcbind();
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tcbind &= ~TCBIND_CURVPE;
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tcbind |= t << TCBIND_CURVPE_SHIFT;
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write_tc_c0_tcbind(tcbind);
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/* Set exclusive TC, non-active, master */
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vpeconf0 = read_vpe_c0_vpeconf0();
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vpeconf0 &= ~(VPECONF0_XTC | VPECONF0_VPA);
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vpeconf0 |= t << VPECONF0_XTC_SHIFT;
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vpeconf0 |= VPECONF0_MVP;
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write_vpe_c0_vpeconf0(vpeconf0);
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/* Declare TC non-active, non-allocatable & interrupt exempt */
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tcstatus = read_tc_c0_tcstatus();
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tcstatus &= ~(TCSTATUS_A | TCSTATUS_DA);
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tcstatus |= TCSTATUS_IXMT;
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write_tc_c0_tcstatus(tcstatus);
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/* Halt the TC */
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write_tc_c0_tchalt(TCHALT_H);
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/* Allow only 1 TC to execute */
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vpecontrol = read_vpe_c0_vpecontrol();
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vpecontrol &= ~VPECONTROL_TE;
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write_vpe_c0_vpecontrol(vpecontrol);
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/* Copy (most of) Status from VPE 0 */
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status = read_c0_status();
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status &= ~(ST0_IM | ST0_IE | ST0_KSU);
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status |= ST0_CU0;
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write_vpe_c0_status(status);
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/* Copy Config from VPE 0 */
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write_vpe_c0_config(read_c0_config());
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write_vpe_c0_config7(read_c0_config7());
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/* Ensure no software interrupts are pending */
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write_vpe_c0_cause(0);
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/* Sync Count */
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write_vpe_c0_count(read_c0_count());
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}
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/* Leave VPE configuration state */
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clear_c0_mvpcontrol(MVPCONTROL_VPC);
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}
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static void __init cps_smp_setup(void)
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{
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unsigned int ncores, nvpes, core_vpes;
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int c, v;
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u32 core_cfg, *entry_code;
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/* Detect & record VPE topology */
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ncores = mips_cm_numcores();
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pr_info("VPE topology ");
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for (c = nvpes = 0; c < ncores; c++) {
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if (cpu_has_mipsmt && config_enabled(CONFIG_MIPS_MT_SMP)) {
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write_gcr_cl_other(c << CM_GCR_Cx_OTHER_CORENUM_SHF);
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core_cfg = read_gcr_co_config();
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core_vpes = ((core_cfg & CM_GCR_Cx_CONFIG_PVPE_MSK) >>
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CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
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} else {
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core_vpes = 1;
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}
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pr_cont("%c%u", c ? ',' : '{', core_vpes);
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for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
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cpu_data[nvpes + v].core = c;
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#ifdef CONFIG_MIPS_MT_SMP
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cpu_data[nvpes + v].vpe_id = v;
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#endif
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}
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nvpes += core_vpes;
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}
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pr_cont("} total %u\n", nvpes);
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/* Indicate present CPUs (CPU being synonymous with VPE) */
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for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
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set_cpu_possible(v, true);
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set_cpu_present(v, true);
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__cpu_number_map[v] = v;
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__cpu_logical_map[v] = v;
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}
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/* Core 0 is powered up (we're running on it) */
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bitmap_set(core_power, 0, 1);
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/* Disable MT - we only want to run 1 TC per VPE */
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if (cpu_has_mipsmt)
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dmt();
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/* Initialise core 0 */
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init_core();
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/* Patch the start of mips_cps_core_entry to provide the CM base */
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entry_code = (u32 *)&mips_cps_core_entry;
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UASM_i_LA(&entry_code, 3, (long)mips_cm_base);
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/* Make core 0 coherent with everything */
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write_gcr_cl_coherence(0xff);
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}
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static void __init cps_prepare_cpus(unsigned int max_cpus)
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{
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mips_mt_set_cpuoptions();
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}
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static void boot_core(struct boot_config *cfg)
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{
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u32 access;
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/* Select the appropriate core */
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write_gcr_cl_other(cfg->core << CM_GCR_Cx_OTHER_CORENUM_SHF);
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/* Set its reset vector */
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write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
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/* Ensure its coherency is disabled */
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write_gcr_co_coherence(0);
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/* Ensure the core can access the GCRs */
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access = read_gcr_access();
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access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + cfg->core);
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write_gcr_access(access);
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/* Copy cfg */
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mips_cps_bootcfg = *cfg;
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if (mips_cpc_present()) {
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/* Select the appropriate core */
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write_cpc_cl_other(cfg->core << CPC_Cx_OTHER_CORENUM_SHF);
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/* Reset the core */
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write_cpc_co_cmd(CPC_Cx_CMD_RESET);
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} else {
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/* Take the core out of reset */
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write_gcr_co_reset_release(0);
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}
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/* The core is now powered up */
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bitmap_set(core_power, cfg->core, 1);
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}
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static void boot_vpe(void *info)
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{
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struct boot_config *cfg = info;
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u32 tcstatus, vpeconf0;
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/* Enter VPE configuration state */
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dvpe();
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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settc(cfg->vpe);
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/* Set the TC restart PC */
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write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
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/* Activate the TC, allow interrupts */
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tcstatus = read_tc_c0_tcstatus();
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tcstatus &= ~TCSTATUS_IXMT;
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tcstatus |= TCSTATUS_A;
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write_tc_c0_tcstatus(tcstatus);
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/* Clear the TC halt bit */
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write_tc_c0_tchalt(0);
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/* Activate the VPE */
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vpeconf0 = read_vpe_c0_vpeconf0();
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vpeconf0 |= VPECONF0_VPA;
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write_vpe_c0_vpeconf0(vpeconf0);
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/* Set the stack & global pointer registers */
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write_tc_gpr_sp(cfg->sp);
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write_tc_gpr_gp(cfg->gp);
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/* Leave VPE configuration state */
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clear_c0_mvpcontrol(MVPCONTROL_VPC);
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/* Enable other VPEs to execute */
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evpe(EVPE_ENABLE);
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}
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static void cps_boot_secondary(int cpu, struct task_struct *idle)
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{
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struct boot_config cfg;
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unsigned int remote;
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int err;
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cfg.core = cpu_data[cpu].core;
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cfg.vpe = cpu_vpe_id(&cpu_data[cpu]);
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cfg.pc = (unsigned long)&smp_bootstrap;
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cfg.sp = __KSTK_TOS(idle);
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cfg.gp = (unsigned long)task_thread_info(idle);
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if (!test_bit(cfg.core, core_power)) {
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/* Boot a VPE on a powered down core */
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boot_core(&cfg);
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return;
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}
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if (cfg.core != current_cpu_data.core) {
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/* Boot a VPE on another powered up core */
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for (remote = 0; remote < NR_CPUS; remote++) {
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if (cpu_data[remote].core != cfg.core)
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continue;
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if (cpu_online(remote))
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break;
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}
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BUG_ON(remote >= NR_CPUS);
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err = smp_call_function_single(remote, boot_vpe, &cfg, 1);
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if (err)
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panic("Failed to call remote CPU\n");
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return;
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}
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BUG_ON(!cpu_has_mipsmt);
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/* Boot a VPE on this core */
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boot_vpe(&cfg);
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}
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static void cps_init_secondary(void)
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{
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/* Disable MT - we only want to run 1 TC per VPE */
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if (cpu_has_mipsmt)
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dmt();
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/* TODO: revisit this assumption once hotplug is implemented */
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if (cpu_vpe_id(¤t_cpu_data) == 0)
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init_core();
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change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
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STATUSF_IP6 | STATUSF_IP7);
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}
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static void cps_smp_finish(void)
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{
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write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* If we have an FPU, enroll ourselves in the FPU-full mask */
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if (cpu_has_fpu)
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cpu_set(smp_processor_id(), mt_fpu_cpumask);
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#endif /* CONFIG_MIPS_MT_FPAFF */
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local_irq_enable();
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}
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static void cps_cpus_done(void)
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{
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}
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static struct plat_smp_ops cps_smp_ops = {
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.smp_setup = cps_smp_setup,
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.prepare_cpus = cps_prepare_cpus,
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.boot_secondary = cps_boot_secondary,
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.init_secondary = cps_init_secondary,
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.smp_finish = cps_smp_finish,
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.send_ipi_single = gic_send_ipi_single,
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.send_ipi_mask = gic_send_ipi_mask,
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.cpus_done = cps_cpus_done,
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};
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int register_cps_smp_ops(void)
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{
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if (!mips_cm_present()) {
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pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
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return -ENODEV;
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}
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/* check we have a GIC - we need one for IPIs */
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if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
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pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
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return -ENODEV;
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}
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register_smp_ops(&cps_smp_ops);
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return 0;
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}
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