602 lines
16 KiB
C
602 lines
16 KiB
C
/*
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* linux/arch/arm/mach-imx/dma.c
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*
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* imx DMA registration and IRQ dispatching
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* 2004-03-03 Sascha Hauer <sascha@saschahauer.de>
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* initial version heavily inspired by
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* linux/arch/arm/mach-pxa/dma.c
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*
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* 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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* Changed to support scatter gather DMA
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* by taking Russell's code from RiscPC
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*
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* 2006-05-31 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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* Corrected error handling code.
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*
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*/
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#undef DEBUG
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/hardware.h>
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#include <asm/dma.h>
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#include <asm/arch/imx-dma.h>
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struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
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/*
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* imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
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* @dma_ch: i.MX DMA channel number
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* @lastcount: number of bytes transferred during last transfer
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*
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* Functions prepares DMA controller for next sg data chunk transfer.
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* The @lastcount argument informs function about number of bytes transferred
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* during last block. Zero value can be used for @lastcount to setup DMA
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* for the first chunk.
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*/
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static inline int imx_dma_sg_next(imx_dmach_t dma_ch, unsigned int lastcount)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
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unsigned int nextcount;
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unsigned int nextaddr;
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if (!imxdma->name) {
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printk(KERN_CRIT "%s: called for not allocated channel %d\n",
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__FUNCTION__, dma_ch);
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return 0;
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}
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imxdma->resbytes -= lastcount;
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if (!imxdma->sg) {
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pr_debug("imxdma%d: no sg data\n", dma_ch);
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return 0;
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}
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imxdma->sgbc += lastcount;
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if ((imxdma->sgbc >= imxdma->sg->length) || !imxdma->resbytes) {
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if ((imxdma->sgcount <= 1) || !imxdma->resbytes) {
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pr_debug("imxdma%d: sg transfer limit reached\n",
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dma_ch);
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imxdma->sgcount=0;
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imxdma->sg = NULL;
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return 0;
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} else {
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imxdma->sgcount--;
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imxdma->sg++;
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imxdma->sgbc = 0;
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}
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}
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nextcount = imxdma->sg->length - imxdma->sgbc;
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nextaddr = imxdma->sg->dma_address + imxdma->sgbc;
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if(imxdma->resbytes < nextcount)
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nextcount = imxdma->resbytes;
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if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
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DAR(dma_ch) = nextaddr;
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else
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SAR(dma_ch) = nextaddr;
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CNTR(dma_ch) = nextcount;
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pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, size 0x%08x\n",
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dma_ch, DAR(dma_ch), SAR(dma_ch), CNTR(dma_ch));
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return nextcount;
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}
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/*
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* imx_dma_setup_sg_base - scatter-gather DMA emulation
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* @dma_ch: i.MX DMA channel number
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* @sg: pointer to the scatter-gather list/vector
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* @sgcount: scatter-gather list hungs count
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*
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* Functions sets up i.MX DMA state for emulated scatter-gather transfer
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* and sets up channel registers to be ready for the first chunk
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*/
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static int
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imx_dma_setup_sg_base(imx_dmach_t dma_ch,
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struct scatterlist *sg, unsigned int sgcount)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
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imxdma->sg = sg;
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imxdma->sgcount = sgcount;
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imxdma->sgbc = 0;
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return imx_dma_sg_next(dma_ch, 0);
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}
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/**
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* imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from device transfer
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* @dma_ch: i.MX DMA channel number
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* @dma_address: the DMA/physical memory address of the linear data block
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* to transfer
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* @dma_length: length of the data block in bytes
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* @dev_addr: physical device port address
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* @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
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* or %DMA_MODE_WRITE from memory to the device
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*
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* The function setups DMA channel source and destination addresses for transfer
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* specified by provided parameters. The scatter-gather emulation is disabled,
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* because linear data block
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* form the physical address range is transferred.
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* Return value: if incorrect parameters are provided -%EINVAL.
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* Zero indicates success.
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*/
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int
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imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
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unsigned int dma_length, unsigned int dev_addr,
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dmamode_t dmamode)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
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imxdma->sg = NULL;
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imxdma->sgcount = 0;
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imxdma->dma_mode = dmamode;
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imxdma->resbytes = dma_length;
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if (!dma_address) {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
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dma_ch);
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return -EINVAL;
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}
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if (!dma_length) {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
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dma_ch);
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return -EINVAL;
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}
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if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
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pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for read\n",
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dma_ch, (unsigned int)dma_address, dma_length,
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dev_addr);
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SAR(dma_ch) = dev_addr;
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DAR(dma_ch) = (unsigned int)dma_address;
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} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
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pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for write\n",
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dma_ch, (unsigned int)dma_address, dma_length,
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dev_addr);
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SAR(dma_ch) = (unsigned int)dma_address;
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DAR(dma_ch) = dev_addr;
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} else {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
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dma_ch);
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return -EINVAL;
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}
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CNTR(dma_ch) = dma_length;
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return 0;
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}
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/**
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* imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
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* @dma_ch: i.MX DMA channel number
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* @sg: pointer to the scatter-gather list/vector
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* @sgcount: scatter-gather list hungs count
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* @dma_length: total length of the transfer request in bytes
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* @dev_addr: physical device port address
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* @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
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* or %DMA_MODE_WRITE from memory to the device
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*
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* The function sets up DMA channel state and registers to be ready for transfer
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* specified by provided parameters. The scatter-gather emulation is set up
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* according to the parameters.
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*
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* The full preparation of the transfer requires setup of more register
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* by the caller before imx_dma_enable() can be called.
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*
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* %BLR(dma_ch) holds transfer burst length in bytes, 0 means 64 bytes
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*
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* %RSSR(dma_ch) has to be set to the DMA request line source %DMA_REQ_xxx
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*
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* %CCR(dma_ch) has to specify transfer parameters, the next settings is typical
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* for linear or simple scatter-gather transfers if %DMA_MODE_READ is specified
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*
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* %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
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*
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* The typical setup for %DMA_MODE_WRITE is specified by next options combination
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*
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* %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
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*
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* Be careful here and do not mistakenly mix source and target device
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* port sizes constants, they are really different:
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* %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
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* %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
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*
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* Return value: if incorrect parameters are provided -%EINVAL.
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* Zero indicates success.
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*/
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int
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imx_dma_setup_sg(imx_dmach_t dma_ch,
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struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length,
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unsigned int dev_addr, dmamode_t dmamode)
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{
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int res;
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struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
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imxdma->sg = NULL;
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imxdma->sgcount = 0;
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imxdma->dma_mode = dmamode;
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imxdma->resbytes = dma_length;
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if (!sg || !sgcount) {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
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dma_ch);
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return -EINVAL;
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}
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if (!sg->length) {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
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dma_ch);
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return -EINVAL;
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}
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if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
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pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for read\n",
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dma_ch, sg, sgcount, dma_length, dev_addr);
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SAR(dma_ch) = dev_addr;
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} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
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pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for write\n",
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dma_ch, sg, sgcount, dma_length, dev_addr);
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DAR(dma_ch) = dev_addr;
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} else {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
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dma_ch);
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return -EINVAL;
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}
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res = imx_dma_setup_sg_base(dma_ch, sg, sgcount);
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if (res <= 0) {
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printk(KERN_ERR "imxdma%d: no sg chunk ready\n", dma_ch);
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return -EINVAL;
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}
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return 0;
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}
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/**
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* imx_dma_setup_handlers - setup i.MX DMA channel end and error notification handlers
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* @dma_ch: i.MX DMA channel number
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* @irq_handler: the pointer to the function called if the transfer
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* ends successfully
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* @err_handler: the pointer to the function called if the premature
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* end caused by error occurs
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* @data: user specified value to be passed to the handlers
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*/
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int
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imx_dma_setup_handlers(imx_dmach_t dma_ch,
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void (*irq_handler) (int, void *),
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void (*err_handler) (int, void *, int),
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void *data)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
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unsigned long flags;
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if (!imxdma->name) {
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printk(KERN_CRIT "%s: called for not allocated channel %d\n",
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__FUNCTION__, dma_ch);
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return -ENODEV;
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}
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local_irq_save(flags);
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DISR = (1 << dma_ch);
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imxdma->irq_handler = irq_handler;
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imxdma->err_handler = err_handler;
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imxdma->data = data;
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local_irq_restore(flags);
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return 0;
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}
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/**
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* imx_dma_enable - function to start i.MX DMA channel operation
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* @dma_ch: i.MX DMA channel number
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*
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* The channel has to be allocated by driver through imx_dma_request()
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* or imx_dma_request_by_prio() function.
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* The transfer parameters has to be set to the channel registers through
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* call of the imx_dma_setup_single() or imx_dma_setup_sg() function
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* and registers %BLR(dma_ch), %RSSR(dma_ch) and %CCR(dma_ch) has to
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* be set prior this function call by the channel user.
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*/
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void imx_dma_enable(imx_dmach_t dma_ch)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
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unsigned long flags;
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pr_debug("imxdma%d: imx_dma_enable\n", dma_ch);
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if (!imxdma->name) {
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printk(KERN_CRIT "%s: called for not allocated channel %d\n",
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__FUNCTION__, dma_ch);
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return;
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}
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local_irq_save(flags);
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DISR = (1 << dma_ch);
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DIMR &= ~(1 << dma_ch);
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CCR(dma_ch) |= CCR_CEN;
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local_irq_restore(flags);
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}
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/**
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* imx_dma_disable - stop, finish i.MX DMA channel operatin
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* @dma_ch: i.MX DMA channel number
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*/
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void imx_dma_disable(imx_dmach_t dma_ch)
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{
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unsigned long flags;
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pr_debug("imxdma%d: imx_dma_disable\n", dma_ch);
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local_irq_save(flags);
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DIMR |= (1 << dma_ch);
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CCR(dma_ch) &= ~CCR_CEN;
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DISR = (1 << dma_ch);
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local_irq_restore(flags);
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}
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/**
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* imx_dma_request - request/allocate specified channel number
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* @dma_ch: i.MX DMA channel number
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* @name: the driver/caller own non-%NULL identification
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*/
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int imx_dma_request(imx_dmach_t dma_ch, const char *name)
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{
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struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
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unsigned long flags;
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/* basic sanity checks */
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if (!name)
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return -EINVAL;
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if (dma_ch >= IMX_DMA_CHANNELS) {
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printk(KERN_CRIT "%s: called for non-existed channel %d\n",
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__FUNCTION__, dma_ch);
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return -EINVAL;
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}
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local_irq_save(flags);
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if (imxdma->name) {
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local_irq_restore(flags);
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return -ENODEV;
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}
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imxdma->name = name;
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imxdma->irq_handler = NULL;
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imxdma->err_handler = NULL;
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imxdma->data = NULL;
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imxdma->sg = NULL;
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local_irq_restore(flags);
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return 0;
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}
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/**
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* imx_dma_free - release previously acquired channel
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* @dma_ch: i.MX DMA channel number
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*/
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void imx_dma_free(imx_dmach_t dma_ch)
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{
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unsigned long flags;
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struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
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if (!imxdma->name) {
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printk(KERN_CRIT
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"%s: trying to free channel %d which is already freed\n",
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__FUNCTION__, dma_ch);
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return;
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}
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local_irq_save(flags);
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/* Disable interrupts */
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DIMR |= (1 << dma_ch);
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CCR(dma_ch) &= ~CCR_CEN;
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imxdma->name = NULL;
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local_irq_restore(flags);
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}
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/**
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* imx_dma_request_by_prio - find and request some of free channels best suiting requested priority
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* @dma_ch: i.MX DMA channel number
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* @name: the driver/caller own non-%NULL identification
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* @prio: one of the hardware distinguished priority level:
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* %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW
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*
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* This function tries to find free channel in the specified priority group
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* if the priority cannot be achieved it tries to look for free channel
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* in the higher and then even lower priority groups.
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*
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* Return value: If there is no free channel to allocate, -%ENODEV is returned.
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* Zero value indicates successful channel allocation.
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*/
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int
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imx_dma_request_by_prio(imx_dmach_t * pdma_ch, const char *name,
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imx_dma_prio prio)
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{
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int i;
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int best;
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switch (prio) {
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case (DMA_PRIO_HIGH):
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best = 8;
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break;
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case (DMA_PRIO_MEDIUM):
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best = 4;
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break;
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case (DMA_PRIO_LOW):
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default:
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best = 0;
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break;
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}
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for (i = best; i < IMX_DMA_CHANNELS; i++) {
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if (!imx_dma_request(i, name)) {
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*pdma_ch = i;
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return 0;
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}
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}
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for (i = best - 1; i >= 0; i--) {
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if (!imx_dma_request(i, name)) {
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*pdma_ch = i;
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return 0;
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}
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}
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printk(KERN_ERR "%s: no free DMA channel found\n", __FUNCTION__);
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return -ENODEV;
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}
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static irqreturn_t dma_err_handler(int irq, void *dev_id)
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{
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int i, disr = DISR;
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struct imx_dma_channel *channel;
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unsigned int err_mask = DBTOSR | DRTOSR | DSESR | DBOSR;
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int errcode;
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DISR = disr & err_mask;
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for (i = 0; i < IMX_DMA_CHANNELS; i++) {
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if(!(err_mask & (1 << i)))
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continue;
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channel = &imx_dma_channels[i];
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errcode = 0;
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if (DBTOSR & (1 << i)) {
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DBTOSR = (1 << i);
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errcode |= IMX_DMA_ERR_BURST;
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}
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if (DRTOSR & (1 << i)) {
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|
DRTOSR = (1 << i);
|
|
errcode |= IMX_DMA_ERR_REQUEST;
|
|
}
|
|
if (DSESR & (1 << i)) {
|
|
DSESR = (1 << i);
|
|
errcode |= IMX_DMA_ERR_TRANSFER;
|
|
}
|
|
if (DBOSR & (1 << i)) {
|
|
DBOSR = (1 << i);
|
|
errcode |= IMX_DMA_ERR_BUFFER;
|
|
}
|
|
|
|
/*
|
|
* The cleaning of @sg field would be questionable
|
|
* there, because its value can help to compute
|
|
* remaining/transferred bytes count in the handler
|
|
*/
|
|
/*imx_dma_channels[i].sg = NULL;*/
|
|
|
|
if (channel->name && channel->err_handler) {
|
|
channel->err_handler(i, channel->data, errcode);
|
|
continue;
|
|
}
|
|
|
|
imx_dma_channels[i].sg = NULL;
|
|
|
|
printk(KERN_WARNING
|
|
"DMA timeout on channel %d (%s) -%s%s%s%s\n",
|
|
i, channel->name,
|
|
errcode&IMX_DMA_ERR_BURST? " burst":"",
|
|
errcode&IMX_DMA_ERR_REQUEST? " request":"",
|
|
errcode&IMX_DMA_ERR_TRANSFER? " transfer":"",
|
|
errcode&IMX_DMA_ERR_BUFFER? " buffer":"");
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t dma_irq_handler(int irq, void *dev_id)
|
|
{
|
|
int i, disr = DISR;
|
|
|
|
pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
|
|
disr);
|
|
|
|
DISR = disr;
|
|
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
|
if (disr & (1 << i)) {
|
|
struct imx_dma_channel *channel = &imx_dma_channels[i];
|
|
if (channel->name) {
|
|
if (imx_dma_sg_next(i, CNTR(i))) {
|
|
CCR(i) &= ~CCR_CEN;
|
|
mb();
|
|
CCR(i) |= CCR_CEN;
|
|
} else {
|
|
if (channel->irq_handler)
|
|
channel->irq_handler(i,
|
|
channel->data);
|
|
}
|
|
} else {
|
|
/*
|
|
* IRQ for an unregistered DMA channel:
|
|
* let's clear the interrupts and disable it.
|
|
*/
|
|
printk(KERN_WARNING
|
|
"spurious IRQ for DMA channel %d\n", i);
|
|
}
|
|
}
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int __init imx_dma_init(void)
|
|
{
|
|
int ret;
|
|
int i;
|
|
|
|
/* reset DMA module */
|
|
DCR = DCR_DRST;
|
|
|
|
ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
|
|
if (ret) {
|
|
printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL);
|
|
if (ret) {
|
|
printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n");
|
|
free_irq(DMA_INT, NULL);
|
|
}
|
|
|
|
/* enable DMA module */
|
|
DCR = DCR_DEN;
|
|
|
|
/* clear all interrupts */
|
|
DISR = (1 << IMX_DMA_CHANNELS) - 1;
|
|
|
|
/* enable interrupts */
|
|
DIMR = (1 << IMX_DMA_CHANNELS) - 1;
|
|
|
|
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
|
imx_dma_channels[i].sg = NULL;
|
|
imx_dma_channels[i].dma_num = i;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
arch_initcall(imx_dma_init);
|
|
|
|
EXPORT_SYMBOL(imx_dma_setup_single);
|
|
EXPORT_SYMBOL(imx_dma_setup_sg);
|
|
EXPORT_SYMBOL(imx_dma_setup_handlers);
|
|
EXPORT_SYMBOL(imx_dma_enable);
|
|
EXPORT_SYMBOL(imx_dma_disable);
|
|
EXPORT_SYMBOL(imx_dma_request);
|
|
EXPORT_SYMBOL(imx_dma_free);
|
|
EXPORT_SYMBOL(imx_dma_request_by_prio);
|
|
EXPORT_SYMBOL(imx_dma_channels);
|