73 lines
1.7 KiB
C
73 lines
1.7 KiB
C
#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <asm/atomic.h>
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#include <asm/system.h>
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#ifdef __HAVE_ARCH_CMPXCHG
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/*
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* This is an implementation of the notion of "decrement a
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* reference count, and return locked if it decremented to zero".
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*
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* This implementation can be used on any architecture that
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* has a cmpxchg, and where atomic->value is an int holding
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* the value of the atomic (i.e. the high bits aren't used
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* for a lock or anything like that).
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*/
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int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock)
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{
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int counter;
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int newcount;
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for (;;) {
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counter = atomic_read(atomic);
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newcount = counter - 1;
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if (!newcount)
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break; /* do it the slow way */
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newcount = cmpxchg(&atomic->counter, counter, newcount);
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if (newcount == counter)
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return 0;
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}
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spin_lock(lock);
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if (atomic_dec_and_test(atomic))
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return 1;
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spin_unlock(lock);
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return 0;
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}
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#else
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/*
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* This is an architecture-neutral, but slow,
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* implementation of the notion of "decrement
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* a reference count, and return locked if it
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* decremented to zero".
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*
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* NOTE NOTE NOTE! This is _not_ equivalent to
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*
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* if (atomic_dec_and_test(&atomic)) {
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* spin_lock(&lock);
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* return 1;
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* }
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* return 0;
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*
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* because the spin-lock and the decrement must be
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* "atomic".
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*
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* This slow version gets the spinlock unconditionally,
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* and releases it if it isn't needed. Architectures
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* are encouraged to come up with better approaches,
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* this is trivially done efficiently using a load-locked
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* store-conditional approach, for example.
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*/
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int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock)
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{
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spin_lock(lock);
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if (atomic_dec_and_test(atomic))
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return 1;
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spin_unlock(lock);
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return 0;
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}
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#endif
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EXPORT_SYMBOL(_atomic_dec_and_lock);
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