320 lines
8.3 KiB
C
320 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// IXP4 GPIO driver
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// Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
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//
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// based on previous work and know-how from:
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// Deepak Saxena <dsaxena@plexity.net>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/bitops.h>
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/* Include that go away with DT transition */
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#include <linux/irqchip/irq-ixp4xx.h>
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#include <asm/mach-types.h>
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#define IXP4XX_REG_GPOUT 0x00
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#define IXP4XX_REG_GPOE 0x04
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#define IXP4XX_REG_GPIN 0x08
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#define IXP4XX_REG_GPIS 0x0C
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#define IXP4XX_REG_GPIT1 0x10
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#define IXP4XX_REG_GPIT2 0x14
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#define IXP4XX_REG_GPCLK 0x18
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#define IXP4XX_REG_GPDBSEL 0x1C
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/*
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* The hardware uses 3 bits to indicate interrupt "style".
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* we clear and set these three bits accordingly. The lower 24
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* bits in two registers (GPIT1 and GPIT2) are used to set up
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* the style for 8 lines each for a total of 16 GPIO lines.
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*/
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#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
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#define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
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#define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
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#define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
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#define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
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#define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0)
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#define IXP4XX_GPIO_STYLE_SIZE 3
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/**
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* struct ixp4xx_gpio - IXP4 GPIO state container
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* @dev: containing device for this instance
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* @fwnode: the fwnode for this GPIO chip
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* @gc: gpiochip for this instance
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* @base: remapped I/O-memory base
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* @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
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* 0: level triggered
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*/
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struct ixp4xx_gpio {
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struct device *dev;
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struct fwnode_handle *fwnode;
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struct gpio_chip gc;
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void __iomem *base;
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unsigned long long irq_edge;
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};
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static void ixp4xx_gpio_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ixp4xx_gpio *g = gpiochip_get_data(gc);
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__raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
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}
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static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ixp4xx_gpio *g = gpiochip_get_data(gc);
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/* ACK when unmasking if not edge-triggered */
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if (!(g->irq_edge & BIT(d->hwirq)))
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ixp4xx_gpio_irq_ack(d);
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irq_chip_unmask_parent(d);
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}
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static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ixp4xx_gpio *g = gpiochip_get_data(gc);
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int line = d->hwirq;
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unsigned long flags;
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u32 int_style;
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u32 int_reg;
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u32 val;
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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irq_set_handler_locked(d, handle_edge_irq);
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int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
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g->irq_edge |= BIT(d->hwirq);
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break;
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case IRQ_TYPE_EDGE_RISING:
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irq_set_handler_locked(d, handle_edge_irq);
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int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
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g->irq_edge |= BIT(d->hwirq);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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irq_set_handler_locked(d, handle_edge_irq);
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int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
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g->irq_edge |= BIT(d->hwirq);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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irq_set_handler_locked(d, handle_level_irq);
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int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
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g->irq_edge &= ~BIT(d->hwirq);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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irq_set_handler_locked(d, handle_level_irq);
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int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
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g->irq_edge &= ~BIT(d->hwirq);
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break;
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default:
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return -EINVAL;
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}
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if (line >= 8) {
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/* pins 8-15 */
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line -= 8;
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int_reg = IXP4XX_REG_GPIT2;
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} else {
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/* pins 0-7 */
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int_reg = IXP4XX_REG_GPIT1;
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}
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spin_lock_irqsave(&g->gc.bgpio_lock, flags);
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/* Clear the style for the appropriate pin */
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val = __raw_readl(g->base + int_reg);
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val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE));
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__raw_writel(val, g->base + int_reg);
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__raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS);
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/* Set the new style */
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val = __raw_readl(g->base + int_reg);
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val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
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__raw_writel(val, g->base + int_reg);
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/* Force-configure this line as an input */
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val = __raw_readl(g->base + IXP4XX_REG_GPOE);
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val |= BIT(d->hwirq);
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__raw_writel(val, g->base + IXP4XX_REG_GPOE);
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spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);
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/* This parent only accept level high (asserted) */
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return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
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}
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static struct irq_chip ixp4xx_gpio_irqchip = {
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.name = "IXP4GPIO",
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.irq_ack = ixp4xx_gpio_irq_ack,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = ixp4xx_gpio_irq_unmask,
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.irq_set_type = ixp4xx_gpio_irq_set_type,
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};
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static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
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unsigned int child,
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unsigned int child_type,
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unsigned int *parent,
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unsigned int *parent_type)
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{
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/* All these interrupts are level high in the CPU */
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*parent_type = IRQ_TYPE_LEVEL_HIGH;
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/* GPIO lines 0..12 have dedicated IRQs */
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if (child == 0) {
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*parent = 6;
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return 0;
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}
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if (child == 1) {
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*parent = 7;
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return 0;
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}
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if (child >= 2 && child <= 12) {
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*parent = child + 17;
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return 0;
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}
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return -EINVAL;
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}
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static int ixp4xx_gpio_probe(struct platform_device *pdev)
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{
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unsigned long flags;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct irq_domain *parent;
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struct resource *res;
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struct ixp4xx_gpio *g;
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struct gpio_irq_chip *girq;
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int ret;
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g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
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if (!g)
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return -ENOMEM;
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g->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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g->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(g->base))
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return PTR_ERR(g->base);
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/*
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* When we convert to device tree we will simply look up the
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* parent irqdomain using irq_find_host(parent) as parent comes
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* from IRQCHIP_DECLARE(), then use of_node_to_fwnode() to get
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* the fwnode. For now we need this boardfile style code.
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*/
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if (np) {
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struct device_node *irq_parent;
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irq_parent = of_irq_find_parent(np);
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if (!irq_parent) {
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dev_err(dev, "no IRQ parent node\n");
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return -ENODEV;
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}
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parent = irq_find_host(irq_parent);
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if (!parent) {
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dev_err(dev, "no IRQ parent domain\n");
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return -ENODEV;
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}
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g->fwnode = of_node_to_fwnode(np);
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} else {
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parent = ixp4xx_get_irq_domain();
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g->fwnode = irq_domain_alloc_fwnode(&res->start);
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if (!g->fwnode) {
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dev_err(dev, "no domain base\n");
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return -ENODEV;
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}
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}
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/*
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* Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on
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* specific machines.
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*/
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if (machine_is_dsmg600() || machine_is_nas100d())
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__raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
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/*
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* This is a very special big-endian ARM issue: when the IXP4xx is
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* run in big endian mode, all registers in the machine are switched
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* around to the CPU-native endianness. As you see mostly in the
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* driver we use __raw_readl()/__raw_writel() to access the registers
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* in the appropriate order. With the GPIO library we need to specify
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* byte order explicitly, so this flag needs to be set when compiling
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* for big endian.
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*/
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#if defined(CONFIG_CPU_BIG_ENDIAN)
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flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
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#else
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flags = 0;
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#endif
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/* Populate and register gpio chip */
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ret = bgpio_init(&g->gc, dev, 4,
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g->base + IXP4XX_REG_GPIN,
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g->base + IXP4XX_REG_GPOUT,
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NULL,
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NULL,
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g->base + IXP4XX_REG_GPOE,
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flags);
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if (ret) {
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dev_err(dev, "unable to init generic GPIO\n");
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return ret;
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}
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g->gc.ngpio = 16;
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g->gc.label = "IXP4XX_GPIO_CHIP";
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/*
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* TODO: when we have migrated to device tree and all GPIOs
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* are fetched using phandles, set this to -1 to get rid of
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* the fixed gpiochip base.
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*/
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g->gc.base = 0;
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g->gc.parent = &pdev->dev;
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g->gc.owner = THIS_MODULE;
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girq = &g->gc.irq;
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girq->chip = &ixp4xx_gpio_irqchip;
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girq->fwnode = g->fwnode;
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girq->parent_domain = parent;
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girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq;
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girq->handler = handle_bad_irq;
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girq->default_type = IRQ_TYPE_NONE;
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ret = devm_gpiochip_add_data(dev, &g->gc, g);
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if (ret) {
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dev_err(dev, "failed to add SoC gpiochip\n");
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return ret;
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}
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platform_set_drvdata(pdev, g);
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dev_info(dev, "IXP4 GPIO registered\n");
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return 0;
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}
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static const struct of_device_id ixp4xx_gpio_of_match[] = {
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{
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.compatible = "intel,ixp4xx-gpio",
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},
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{},
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};
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static struct platform_driver ixp4xx_gpio_driver = {
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.driver = {
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.name = "ixp4xx-gpio",
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.of_match_table = of_match_ptr(ixp4xx_gpio_of_match),
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},
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.probe = ixp4xx_gpio_probe,
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};
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builtin_platform_driver(ixp4xx_gpio_driver);
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